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    Manufacturing method of package structure having conductive shield
    1.
    发明授权
    Manufacturing method of package structure having conductive shield 有权

    公开(公告)号：US10276510B2

    公开(公告)日：2019-04-30

    申请号：US15713717

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L21/56 ,  H01L23/552 ,  H01L23/00

    Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

    Semiconductor package utilizing tape to reinforce fixing of leads to die pad
    2.
    发明授权
    Semiconductor package utilizing tape to reinforce fixing of leads to die pad 有权
    使用胶带的半导体封装，以加强引线到芯片焊盘的固定

    公开(公告)号：US08541870B1

    公开(公告)日：2013-09-24

    申请号：US13645289

    申请日：2012-10-04

    Applicant: Powertech Technology Inc.

    Inventor： Wen-Jeng Fan ,  Che-Min Chu ,  Wei-Min Chen

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00

    Abstract: Disclosed is a semiconductor package utilizing a tape to reinforce fixing of leads to a die pad having a through hole. The package primarily comprises a leadframe having the plurality of leads and the die pad, a tape, at least a chip, and an encapsulant. The die pad. The tape is attached beneath the leadframe adjacent to the inner fingers of the leads to fix the leads and the die pad for wire-bonding. Additionally, the tape does not completely cover the through hole. The chip is disposed on the leads and the die pad and electrically connected to the inner fingers. The encapsulant encapsulates the die pad, the tape and the chip with the leads being insulatedly bonded where the encapsulant further completely fills into the through hole through its opening without completely covered by the tape.

    Abstract translation: 公开了一种利用带子来加强将引线固定到具有通孔的管芯焊盘的半导体封装。 封装主要包括具有多个引线和管芯焊盘的引线框，至少芯片和密封剂的带。 芯片垫 带子连接在引线框架的下方，与引线的内指相邻，以固定引线和芯片焊盘以进行引线接合。 此外，磁带不完全覆盖通孔。 芯片设置在引线和芯片焊盘上，并与内指电连接。 密封剂封装芯片焊盘，磁带和芯片，引线绝缘地结合在一起，其中密封剂通过其开口进一步完全填充到通孔中，而不完全被磁带覆盖。

    MANUFACTURING METHOD OF PACKAGE STRUCTURE
    3.
    发明申请
    MANUFACTURING METHOD OF PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20190096821A1

    公开(公告)日：2019-03-28

    申请号：US15713717

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56

    Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

    Stacked chip package structure and manufacturing method thereof
    5.
    发明授权
    Stacked chip package structure and manufacturing method thereof 有权

    公开(公告)号：US10950557B2

    公开(公告)日：2021-03-16

    申请号：US16780921

    申请日：2020-02-04

    Applicant: Powertech Technology Inc.

    Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

    IPC: H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

    STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200176395A1

    公开(公告)日：2020-06-04

    申请号：US16780921

    申请日：2020-02-04

    Applicant: Powertech Technology Inc.

    Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

    IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00

    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

    Package structure and chip structure
    8.
    发明授权
    Package structure and chip structure 有权

    公开(公告)号：US10607860B2

    公开(公告)日：2020-03-31

    申请号：US15713708

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L21/683

    Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.

    PACKAGE STRUCTURE AND CHIP STRUCTURE
    9.
    发明申请
    PACKAGE STRUCTURE AND CHIP STRUCTURE 审中-公开

    公开(公告)号：US20190096699A1

    公开(公告)日：2019-03-28

    申请号：US15713708

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78

    Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.

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