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公开(公告)号:US10276510B2
公开(公告)日:2019-04-30
申请号:US15713717
申请日:2017-09-25
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Ji-Cheng Lin , Che-Min Chu , Chun-Te Lin
IPC: H01L21/56 , H01L23/552 , H01L23/00
Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.
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公开(公告)号:US20200243449A1
公开(公告)日:2020-07-30
申请号:US16261566
申请日:2019-01-30
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Wen-Jeng Fan
Abstract: A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.
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公开(公告)号:US10431549B2
公开(公告)日:2019-10-01
申请号:US15867670
申请日:2018-01-10
Applicant: Powertech Technology Inc.
Inventor: Chien-Wen Huang , Chia-Wei Chiang , Wen-Jeng Fan , Li-Chih Fang
IPC: H01L23/495 , H01L23/538 , H01L25/065 , H01L25/00 , H01L23/00 , H01L23/31 , H01L21/56 , H01L21/48 , H01L21/78 , H01L25/10
Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
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公开(公告)号:US20190096821A1
公开(公告)日:2019-03-28
申请号:US15713717
申请日:2017-09-25
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Ji-Cheng Lin , Che-Min Chu , Chun-Te Lin
IPC: H01L23/552 , H01L23/00 , H01L21/56
Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.
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公开(公告)号:US20200013721A1
公开(公告)日:2020-01-09
申请号:US16030826
申请日:2018-07-09
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Wen-Jeng Fan
IPC: H01L23/538 , H01L23/13 , H01L23/31 , H01L23/00 , H01L21/56 , H01L25/10 , H01L25/00 , H01L23/367 , H01L23/552 , H01L21/683
Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.
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公开(公告)号:US20200006274A1
公开(公告)日:2020-01-02
申请号:US16022707
申请日:2018-06-29
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Wen-Jeng Fan
Abstract: A semiconductor package includes a semiconductor die, a first redistribution structure, a conductive structure, and an insulating encapsulant. The first redistribution structure includes a dielectric protrusion. The first redistribution structure includes a die attach region and a peripheral region surrounding the die attach region. The semiconductor die is disposed on the first redistribution structure within the die attach region. The dielectric protrusion is disposed in the peripheral region and extends in a thickness direction of the semiconductor die. The conductive structure is disposed on the first redistribution structure within the in the peripheral region and encapsulates the semiconductor dielectric protrusion. The conductive structure is electrically coupled to the first redistribution structure and the semiconductor die. The insulator is disposed on the first redistribution structure and encapsulates the semiconductor die and the conductive structure.
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公开(公告)号:US20190214347A1
公开(公告)日:2019-07-11
申请号:US15867670
申请日:2018-01-10
Applicant: Powertech Technology Inc.
Inventor: Chien-Wen Huang , Chia-Wei Chiang , Wen-Jeng Fan , Li-Chih Fang
IPC: H01L23/538 , H01L25/10 , H01L25/065 , H01L25/00 , H01L23/00 , H01L23/31 , H01L21/56 , H01L21/48 , H01L21/78
Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
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公开(公告)号:US20200243461A1
公开(公告)日:2020-07-30
申请号:US16261561
申请日:2019-01-30
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Wen-Jeng Fan
Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a bumpless die including a plurality of conductive pads, a conductive connector disposed aside the bumpless die and electrically coupled to the bumpless die, an insulating encapsulation encapsulating the bumpless die and the conductive connector, a circuit layer electrically connected to the bumpless die and the conductive connector, and a front side redistribution layer disposed on the circuit layer and including a finer line and spacing routing than the circuit layer. The circuit layer includes a conductive pattern disposed on the insulating encapsulation and extending along a thickness direction of the bumpless die to be connected to the conductive pads of the bumpless die, and a dielectric pattern disposed on the insulating encapsulation and laterally covering the conductive pattern.
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公开(公告)号:US10607860B2
公开(公告)日:2020-03-31
申请号:US15713708
申请日:2017-09-25
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Ji-Cheng Lin , Che-Min Chu , Chun-Te Lin
IPC: H01L21/56 , H01L21/48 , H01L21/78 , H01L23/31 , H01L23/552 , H01L23/00 , H01L21/683
Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.
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公开(公告)号:US10593629B2
公开(公告)日:2020-03-17
申请号:US16030826
申请日:2018-07-09
Applicant: Powertech Technology Inc.
Inventor: Chia-Wei Chiang , Li-Chih Fang , Wen-Jeng Fan
IPC: H01L23/538 , H01L23/31 , H01L23/00 , H01L21/56 , H01L25/10 , H01L25/00 , H01L23/367 , H01L23/552 , H01L21/683 , H01L23/13
Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.
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