Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US15867670Application Date: 2018-01-10
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Publication No.: US10431549B2Publication Date: 2019-10-01
- Inventor: Chien-Wen Huang , Chia-Wei Chiang , Wen-Jeng Fan , Li-Chih Fang
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: JCIPRNET
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/538 ; H01L25/065 ; H01L25/00 ; H01L23/00 ; H01L23/31 ; H01L21/56 ; H01L21/48 ; H01L21/78 ; H01L25/10

Abstract:
A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
Public/Granted literature
- US20190214347A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2019-07-11
Information query
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