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    Package structure
    2.
    发明授权
    Package structure 有权
    包装结构

    公开(公告)号：US09324651B1

    公开(公告)日：2016-04-26

    申请号：US14574408

    申请日：2014-12-18

    Applicant: Powertech Technology Inc.

    Inventor： Wen-Jeng Fan

    IPC: H01L23/02 ,  H01L23/522 ,  H01L23/00

    CPC classification number: H01L24/49 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/183 ,  H01L2924/00012 ,  H01L2224/45099

    Abstract: A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface and bonding pads disposed on the active surface. The substrate includes first and second solder masks, first and second patterned circuit layers and a core layer having a first surface and a second surface. The first patterned circuit layer is disposed on the first solder mask. The core layer disposed on the first solder mask with the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the first solder mask exposes the bonding pads. The second patterned circuit layer disposed on the second surface. The second solder mask partially covers the second patterned circuit layer. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate.

    Abstract translation: 封装结构包括芯片，基板，电线和模塑料。 芯片包括有源表面，背面和设置在有源表面上的接合焊盘。 衬底包括第一和第二焊料掩模，第一和第二图案化电路层以及具有第一表面和第二表面的芯层。 第一图案化电路层设置在第一焊接掩模上。 设置在具有第一表面的第一焊料掩模上的芯层部分地暴露第一图案化电路层。 用第一焊接掩模布置在有源表面上的衬底暴露接合焊盘。 第二图案化电路层设置在第二表面上。 第二焊接掩模部分地覆盖第二图案化电路层。 导线连接在第一图案化电路层和接合焊盘之间。 模塑料覆盖芯片，导线和基板。

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200335456A1

    公开(公告)日：2020-10-22

    申请号：US16384940

    申请日：2019-04-16

    Applicant: Powertech Technology Inc.

    Inventor： Wen-Jeng Fan

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

    Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed adjacent to the semiconductor chip, an insulating encapsulation covering the semiconductor chip and the conductive element, a redistribution structure disposed on the semiconductor chip and the conductive element, and a first buffer layer disposed between the redistribution structure and the insulating encapsulation is provided. The semiconductor chip is electrically coupled to the conductive element through the redistribution structure. The first buffer layer covers the semiconductor chip and the conductive element. A manufacturing method of a semiconductor package is also provided.

    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200243449A1

    公开(公告)日：2020-07-30

    申请号：US16261566

    申请日：2019-01-30

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Wen-Jeng Fan

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

    Abstract: A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.

    Semiconductor package and manufacturing method thereof
    5.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US10431549B2

    公开(公告)日：2019-10-01

    申请号：US15867670

    申请日：2018-01-10

    Applicant: Powertech Technology Inc.

    Inventor： Chien-Wen Huang ,  Chia-Wei Chiang ,  Wen-Jeng Fan ,  Li-Chih Fang

    IPC: H01L23/495 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L25/10

    Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200328144A1

    公开(公告)日：2020-10-15

    申请号：US16382229

    申请日：2019-04-12

    Applicant: Powertech Technology Inc.

    Inventor： Wen-Jeng Fan ,  Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/56 ,  H01L21/48

    Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

    PACKAGE STRUCTURE
    9.
    发明申请
    PACKAGE STRUCTURE 审中-公开
    包装结构

    公开(公告)号：US20160163624A1

    公开(公告)日：2016-06-09

    申请号：US14564091

    申请日：2014-12-09

    Applicant: Powertech Technology Inc.

    Inventor： Wen-Jeng Fan

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

    CPC classification number: H01L23/49811 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/09 ,  H01L24/32 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2224/45099

    Abstract: A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface opposite to the active surface and bonding pads disposed on the active surface. The substrate includes a first solder mask, a first patterned circuit layer and a core layer having a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The first solder mask disposed on the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the second surface exposes the bonding pads. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate. A top surface of the molding compound is coplanar with a top surface of the first solder mask.

    Abstract translation: 封装结构包括芯片，基板，电线和模塑料。 芯片包括有源表面，与有源表面相对的后表面和设置在有源表面上的焊盘。 衬底包括第一焊料掩模，第一图案化电路层和具有第一表面和与第一表面相对的第二表面的芯层。 第一图案化电路层设置在第一表面上。 布置在第一表面上的第一焊料掩模部分地暴露第一图案化电路层。 设置在具有第二表面的有源表面上的衬底暴露接合焊盘。 电线连接在第一图案化电路层和接合焊盘之间。 模塑料覆盖芯片，导线和基板。 模塑料的顶表面与第一焊接掩模的顶表面共面。

    Semiconductor package utilizing tape to reinforce fixing of leads to die pad
    10.
    发明授权
    Semiconductor package utilizing tape to reinforce fixing of leads to die pad 有权
    使用胶带的半导体封装，以加强引线到芯片焊盘的固定

    公开(公告)号：US08541870B1

    公开(公告)日：2013-09-24

    申请号：US13645289

    申请日：2012-10-04

    Applicant: Powertech Technology Inc.

    Inventor： Wen-Jeng Fan ,  Che-Min Chu ,  Wei-Min Chen

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00

    Abstract: Disclosed is a semiconductor package utilizing a tape to reinforce fixing of leads to a die pad having a through hole. The package primarily comprises a leadframe having the plurality of leads and the die pad, a tape, at least a chip, and an encapsulant. The die pad. The tape is attached beneath the leadframe adjacent to the inner fingers of the leads to fix the leads and the die pad for wire-bonding. Additionally, the tape does not completely cover the through hole. The chip is disposed on the leads and the die pad and electrically connected to the inner fingers. The encapsulant encapsulates the die pad, the tape and the chip with the leads being insulatedly bonded where the encapsulant further completely fills into the through hole through its opening without completely covered by the tape.

    Abstract translation: 公开了一种利用带子来加强将引线固定到具有通孔的管芯焊盘的半导体封装。 封装主要包括具有多个引线和管芯焊盘的引线框，至少芯片和密封剂的带。 芯片垫 带子连接在引线框架的下方，与引线的内指相邻，以固定引线和芯片焊盘以进行引线接合。 此外，磁带不完全覆盖通孔。 芯片设置在引线和芯片焊盘上，并与内指电连接。 密封剂封装芯片焊盘，磁带和芯片，引线绝缘地结合在一起，其中密封剂通过其开口进一步完全填充到通孔中，而不完全被磁带覆盖。

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