公开(公告)号：US12154863B2

公开(公告)日：2024-11-26

申请号：US17454742

申请日：2021-11-12

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/762 ,  H01L23/66 ,  H01Q1/22

Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.

公开(公告)号：US11532575B2

公开(公告)日：2022-12-20

申请号：US16562442

申请日：2019-09-06

Applicant: Powertech Technology Inc.

Inventor： Han-Wen Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/78 ,  H01L23/552

Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US11309296B2

公开(公告)日：2022-04-19

申请号：US16687713

申请日：2019-11-19

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Wen-Hsiung Chang

IPC: H01L25/16 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

公开(公告)号：US20210202440A1

公开(公告)日：2021-07-01

申请号：US17099801

申请日：2020-11-17

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L23/36 ,  H01L25/00

Abstract: A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is electrically connected to the bridge die. The second encapsulant covers the first active die and the second active die. The redistribution circuit structure is electrically connected to the through silicon via die. The through silicon via die is disposed between the first active die and the redistribution circuit structure. A manufacturing method of a packaging structure is also provided.

公开(公告)号：US20210202364A1

公开(公告)日：2021-07-01

申请号：US16953362

申请日：2020-11-20

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Chia-Yu Hung ,  Nan-Chun Lin

IPC: H01L23/498 ,  H01L23/16 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00

Abstract: A package structure including a first circuit board, a second circuit board, an encapsulant, a plurality of conductive terminals, and a package device is provided. The first circuit board has a first top surface and a first bottom surface opposite to each other. The second circuit board has a second top surface and a second bottom surface opposite to each other. The encapsulant encapsulates the first and second circuit boards. The conductive terminals are disposed on the first or second bottom surface and electrically connected to the first or second circuit board. The package device is disposed on the first or second top surface and electrically connected to the first and second circuit boards. The package device includes a first chip, a second chip, a chip encapsulant, a circuit layer, and a plurality of conductive package terminals. A manufacturing method of a package structure is also provided.

公开(公告)号：US20210202268A1

公开(公告)日：2021-07-01

申请号：US17124448

申请日：2020-12-16

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

Abstract: A package device and a manufacturing method thereof are provided. The manufacturing method of the package device includes providing a substrate and forming a redistribution layer on the substrate. The substrate has at least one device region and a non-device region. The redistribution layer includes at least one inspection structure and at least one wire structure. The wire structure is disposed in the device region, a part of the inspection structure and a part of the wire structure are formed of a same layer, and the inspection structure has a trench exposing the part of the inspection structure.

公开(公告)号：US11024603B2

公开(公告)日：2021-06-01

申请号：US16386276

申请日：2019-04-17

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Chih Chen ,  Hung-Hsin Hsu ,  Yuan-Fu Lan ,  Chi-An Wang ,  Hsien-Wen Hsu

IPC: H01L25/065 ,  H01L21/76 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56

Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.

公开(公告)号：US20210098517A1

公开(公告)日：2021-04-01

申请号：US16856011

申请日：2020-04-22

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L27/146

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

公开(公告)号：US20210074661A1

公开(公告)日：2021-03-11

申请号：US16740496

申请日：2020-01-13

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US20210074645A1

公开(公告)日：2021-03-11

申请号：US16679326

申请日：2019-11-11

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Pei-Chun Tsai ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A chip package structure using silicon interposer as interconnection bridge lifts multi-dies above the fan-out molding package embedded with premade Si interposer interconnection bridge under the multi-die space. The interconnection bridge connects the multi-dies through fine pitch high I/O interconnection. A first RDL and a second RDL are further disposed on top side and bottom side of the fan-out molding package, further providing connection for the multi-dies to a substrate via the connection routing inside the fan-out molding package.