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公开(公告)号：US20240347438A1
公开(公告)日：2024-10-17
申请号：US18632221
申请日：2024-04-10
发明人： Shang-Yu Chang Chien
IPC分类号： H01L23/498 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L23/49838 , H01L23/3128 , H01L24/94 , H01L25/0655 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/1815
摘要： A package structure including a redistributed circuit structure, a plurality of chips, a second encapsulant, a plurality of supporting members, a first encapsulant, and a plurality of connection terminals are provided. The redistributed circuit structure has a first surface and a second surface opposite thereto. The chips are disposed on the second surface of the redistributed circuit structure. The second encapsulant is disposed on the second surface of the redistributed circuit structure and covers the chips. The supporting members are disposed on the first surface of the redistributed circuit structure. The first encapsulant is disposed on the first surface of the redistributed circuit structure and covers the supporting members. The connection terminals are connected to the supporting members.
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公开(公告)号：US20230290730A1
公开(公告)日：2023-09-14
申请号：US18078055
申请日：2022-12-08
IPC分类号： H01L23/538 , H01L23/31 , H01L21/48 , H01L21/56
CPC分类号： H01L23/5381 , H01L23/5383 , H01L23/3128 , H01L21/4857 , H01L21/56 , H01L21/568 , H01L2224/16227 , H01L24/16
摘要： A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, at least one bridge chip, a photosensitive encapsulation layer, a redistribution layer, and at least two active chips. The conductive pillars and the bridge chip are disposed on the substrate. The photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, in which a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. The redistribution layer is disposed on the photosensitive encapsulation layer, the active chips are disposed on the redistribution layer, and the bridge chip is coupled between the active chips.
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公开(公告)号：US20230197647A1
公开(公告)日：2023-06-22
申请号：US18071632
申请日：2022-11-30
IPC分类号： H01L23/66 , H01Q1/52 , H01Q1/22 , H01L23/552 , H01L23/00 , H01L21/56 , H01L23/498
CPC分类号： H01L23/66 , H01Q1/526 , H01Q1/2283 , H01L23/552 , H01L24/16 , H01L24/96 , H01L24/97 , H01L21/561 , H01L23/49838 , H01L2223/6616 , H01L2223/6677 , H01L2224/97 , H01L2224/96 , H01L2224/95001 , H01L2224/16225 , H01L2924/1421 , H01L2924/3025 , H01L23/49816 , H01L23/49822
摘要： Provided is an integrated antenna package structure including a chip, a circuit structure, a shielding body, an encapsulant, a first antenna layer, a dielectric body, and a second antenna layer. The circuit structure is electrically connected to the chip. The shielding body is disposed on the circuit structure and has an accommodating space. The chip is disposed in the accommodating space of the shielding body. The encapsulant is disposed on the circuit structure and covers the chip. The first antenna layer is disposed on the circuit structure and is electrically connected to the circuit structure. The dielectric body is disposed on the encapsulant. The second antenna layer is disposed on the dielectric body. A manufacturing method of the integrated antenna package structure is also provided.
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公开(公告)号：US11545424B2
公开(公告)日：2023-01-03
申请号：US16952084
申请日：2020-11-19
IPC分类号： H01L21/48 , H01L23/498 , H01L23/00 , H01L25/18 , H01L21/56 , H01L21/683 , H01L25/065 , H01L25/16 , H01L25/00 , H01L23/31 , H01L23/538 , H01L23/24 , H01L21/78 , H01L23/16 , H01L23/367 , H01L23/552
摘要： A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.
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公开(公告)号：US11296041B2
公开(公告)日：2022-04-05
申请号：US16698869
申请日：2019-11-27
IPC分类号： H01L23/66 , H01L23/538 , H01L23/00 , H01L21/48 , H01L21/56 , H01L21/683 , H01Q1/22 , H01L23/31 , H01L25/10 , H01L25/00 , H01L21/78 , H01L23/552
摘要： An integrated antenna package structure including a chip package and an antenna device is provided. The antenna device is disposed on the chip package. The chip package includes a chip, an encapsulant, a circuit layer, and a conductive connector. The encapsulant at least directly covers the back side of the chip. The circuit layer is disposed under the encapsulant and electrically connected to the chip. The conductive connector penetrates the encapsulant and is electrically connected to the circuit layer. The antenna device includes a dielectric body, a coupling layer, and an antenna layer. The dielectric body has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The coupling layer is disposed on the second dielectric surface of the dielectric body. The antenna layer is disposed on the first dielectric surface of the dielectric body. The antenna layer is electrically connected to the conductive connector. A manufacturing method of an integrated antenna package structure is also provided.
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公开(公告)号：US11211350B2
公开(公告)日：2021-12-28
申请号：US16521596
申请日：2019-07-25
IPC分类号： H01L21/56 , H01L23/00 , H01L23/29 , H01L23/31 , H01L21/768 , H01L23/522 , H01L23/538 , H01L25/065
摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.
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公开(公告)号：US20200273829A1
公开(公告)日：2020-08-27
申请号：US16521596
申请日：2019-07-25
IPC分类号： H01L23/00 , H01L23/29 , H01L23/31 , H01L23/522 , H01L21/56 , H01L21/768
摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.
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公开(公告)号：US10756065B2
公开(公告)日：2020-08-25
申请号：US16741749
申请日：2020-01-14
IPC分类号： H01L23/48 , H01L25/065 , H01L23/498 , H01L23/00 , H01L21/48 , H01L25/00 , H01L23/31
摘要： A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires. A thinning process is performed to obtain an insulating encapsulant by reducing a thickness of the insulating material until a portion of each of the conductive wires is removed to form a plurality of conductive wire segments, wherein the semiconductor die is electrically insulated from the first redistribution layer after the thinning process. A second redistribution layer is formed on a top surface of the insulating encapsulant, and over the semiconductor die. The second redistribution layer is electrically connected to the first redistribution layer and to the semiconductor die by the plurality of conductive wire segments.
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公开(公告)号：US20200091126A1
公开(公告)日：2020-03-19
申请号：US16687713
申请日：2019-11-19
IPC分类号： H01L25/16 , H01L23/48 , H01L23/498 , H01L21/768 , H01L21/48 , H01L21/56
摘要： A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.
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公开(公告)号：US10522512B2
公开(公告)日：2019-12-31
申请号：US15968769
申请日：2018-05-02
IPC分类号： H01L25/065 , H01L25/00 , H01L21/66 , H01L23/538 , G01R31/28
摘要： A semiconductor package including an ultra-thin redistribution structure, a semiconductor die, a first insulating encapsulant, a semiconductor chip stack, and a second insulating encapsulant is provided. The semiconductor die is disposed on and electrically coupled to the ultra-thin redistribution structure. The first insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor die. The semiconductor chip stack is disposed on the first insulating encapsulant and electrically coupled to the ultra-thin redistribution structure. The second insulating encapsulant is disposed on the ultra-thin redistribution structure and encapsulates the semiconductor chip stack and the first insulating encapsulant. A manufacturing method of a semiconductor package is also provided.
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