Invention Grant
- Patent Title: Package structure and chip structure
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Application No.: US15713708Application Date: 2017-09-25
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Publication No.: US10607860B2Publication Date: 2020-03-31
- Inventor: Chia-Wei Chiang , Li-Chih Fang , Ji-Cheng Lin , Che-Min Chu , Chun-Te Lin
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: JCIPRNET
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L21/48 ; H01L21/78 ; H01L23/31 ; H01L23/552 ; H01L23/00 ; H01L21/683

Abstract:
A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.
Public/Granted literature
- US20190096699A1 PACKAGE STRUCTURE AND CHIP STRUCTURE Public/Granted day:2019-03-28
Information query
IPC分类: