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    MANUFACTURING METHOD OF PACKAGE STRUCTURE
    1.
    发明申请
    MANUFACTURING METHOD OF PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20190096821A1

    公开(公告)日：2019-03-28

    申请号：US15713717

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56

    Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

    Stacked chip package structure and manufacturing method thereof
    3.
    发明授权
    Stacked chip package structure and manufacturing method thereof 有权

    公开(公告)号：US10950557B2

    公开(公告)日：2021-03-16

    申请号：US16780921

    申请日：2020-02-04

    Applicant: Powertech Technology Inc.

    Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

    IPC: H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

    STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200176395A1

    公开(公告)日：2020-06-04

    申请号：US16780921

    申请日：2020-02-04

    Applicant: Powertech Technology Inc.

    Inventor： Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin ,  Chien-Wen Huang

    IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00

    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

    Package structure and chip structure
    6.
    发明授权
    Package structure and chip structure 有权

    公开(公告)号：US10607860B2

    公开(公告)日：2020-03-31

    申请号：US15713708

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L21/683

    Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.

    PACKAGE STRUCTURE AND CHIP STRUCTURE
    7.
    发明申请
    PACKAGE STRUCTURE AND CHIP STRUCTURE 审中-公开

    公开(公告)号：US20190096699A1

    公开(公告)日：2019-03-28

    申请号：US15713708

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78

    Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.

    Manufacturing method of package structure having conductive shield
    9.
    发明授权
    Manufacturing method of package structure having conductive shield 有权

    公开(公告)号：US10276510B2

    公开(公告)日：2019-04-30

    申请号：US15713717

    申请日：2017-09-25

    Applicant: Powertech Technology Inc.

    Inventor： Chia-Wei Chiang ,  Li-Chih Fang ,  Ji-Cheng Lin ,  Che-Min Chu ,  Chun-Te Lin

    IPC: H01L21/56 ,  H01L23/552 ,  H01L23/00

    Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.

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