Invention Grant
- Patent Title: Semiconductor packaging structure and method for packaging semiconductor device
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Application No.: US16987470Application Date: 2020-08-07
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Publication No.: US11302539B2Publication Date: 2022-04-12
- Inventor: Tsung-Han Chiang , Chun-Te Lin
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Burris Law, PLLC
- Priority: TW109115434 20200508
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/31 ; H01L23/29 ; H01L21/683
Abstract:
A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.
Public/Granted literature
- US20210351044A1 SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD FOR PACKAGING SEMICONDUCTOR DEVICE Public/Granted day:2021-11-11
Information query
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