公开(公告)号：US11302539B2

公开(公告)日：2022-04-12

申请号：US16987470

申请日：2020-08-07

Applicant: Powertech Technology Inc.

Inventor： Tsung-Han Chiang ,  Chun-Te Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/29 ,  H01L21/683

Abstract: A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.