公开(公告)号：US11362055B2

公开(公告)日：2022-06-14

申请号：US17096190

申请日：2020-11-12

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L23/00

Abstract: The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.

公开(公告)号：US20200321259A1

公开(公告)日：2020-10-08

申请号：US16417671

申请日：2019-05-21

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L23/31 ,  H01L23/00

Abstract: A semiconductor package structure includes a substrate, a chip, and an encapsulant. The chip is disposed on the substrate. The encapsulant is disposed on the substrate and covers the chip. The encapsulant has a top surface away from the substrate and at least one protruding strip protruding from the top surface.

公开(公告)号：US11694950B2

公开(公告)日：2023-07-04

申请号：US17198653

申请日：2021-03-11

Applicant: Powertech Technology Inc.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/08165 ,  H01L2224/32225

Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

公开(公告)号：US11133291B2

公开(公告)日：2021-09-28

申请号：US16817656

申请日：2020-03-13

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L25/065 ,  H01L23/12 ,  H01L23/538

Abstract: A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.

公开(公告)号：US20210202444A1

公开(公告)日：2021-07-01

申请号：US16817656

申请日：2020-03-13

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Chih-Yen Su ,  Chun-Te Lin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/12

Abstract: A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.