公开(公告)号：US07416980B2

公开(公告)日：2008-08-26

申请号：US11078611

申请日：2005-03-11

Applicant: Ting Zhong ,  Valery Dubin ,  Ming Fang

Inventor： Ting Zhong ,  Valery Dubin ,  Ming Fang

IPC: H01L21/44

CPC classification number: H01L21/2885 ,  H01L21/7685 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2224/05099

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括在衬底上形成阻挡层，其中阻挡层包含钼; 以及在阻挡层上形成无铅互连结构。

公开(公告)号：US20070248794A1

公开(公告)日：2007-10-25

申请号：US11408745

申请日：2006-04-21

Applicant: Florian Gstrein ,  James Blackwell ,  Amlan Majumdar ,  Valery Dubin

Inventor： Florian Gstrein ,  James Blackwell ,  Amlan Majumdar ,  Valery Dubin

IPC: B05D7/22 ,  C23C16/00 ,  B32B9/00 ,  B32B3/10

CPC classification number: H01L23/53276 ,  B82Y10/00 ,  H01L23/49877 ,  H01L2924/0002 ,  Y10T428/24322 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming an opening in a substrate, placing at least one multi-walled CNT within the opening, and forming a carbide layer on the at least one multi-walled CNT.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在基底中形成开口，将至少一个多壁CNT放置在开口内，以及在至少一个多壁CNT上形成碳化物层。

公开(公告)号：US20070155158A1

公开(公告)日：2007-07-05

申请号：US11325774

申请日：2005-12-30

Applicant: Florian Gstrein ,  Valery Dubin ,  Juan Dominguez ,  Adrien Lavoie

Inventor： Florian Gstrein ,  Valery Dubin ,  Juan Dominguez ,  Adrien Lavoie

IPC: H01L21/4763

CPC classification number: H01L21/76877 ,  H01L21/76838 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/75 ,  H01L2924/00

Abstract: A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.

Abstract translation: 一种包括在牺牲衬底上形成单层碳纳米管的互连的方法; 将所述互连件从所述牺牲衬底转移到电路衬底; 以及将所述互连件耦合到所述电路基板上的接触点。 一种方法，包括在第一接触点和第二接触点之间的电路基板上形成纳米管束，所述纳米管限定通过其的腔; 用导电材料填充纳米管束管腔长度的一部分; 以及将所述导电材料耦合到所述第二接触点。 一种包括计算设备的系统，包括微处理器，微处理器耦合到印刷电路板，微处理器包括具有多个电路器件的衬底，该电路器件具有通过包括碳纳米管束的互连结构与多个电路器件形成的电连接。

公开(公告)号：US20070148952A1

公开(公告)日：2007-06-28

申请号：US11318137

申请日：2005-12-23

Applicant: Kevin O'Brien ,  Chin-Chang Cheng ,  Ramanan Chebiam ,  Valery Dubin ,  Sridhar Balakrishnan

Inventor： Kevin O'Brien ,  Chin-Chang Cheng ,  Ramanan Chebiam ,  Valery Dubin ,  Sridhar Balakrishnan

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  B82Y30/00 ,  H01L21/288 ,  H01L21/76874

Abstract: Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.

Abstract translation: 使用利用与催化金属复合的偶联剂和由此形成的结构的化学沉积技术形成的阻挡材料层来制造互连结构的方法。 该制造基本上包括提供介电材料层，其具有从其第一表面延伸到电介质材料中的开口，将该耦合剂粘合到该开口内的电介质材料，以及无电沉积阻挡材料层，其中该无电沉积阻挡材料层 材料粘附到偶联剂的催化金属上。

公开(公告)号：US20060267051A1

公开(公告)日：2006-11-30

申请号：US11136585

申请日：2005-05-25

Applicant: Florian Gstrein ,  Valery Dubin

Inventor： Florian Gstrein ,  Valery Dubin

IPC: H01L29/15

CPC classification number: G01N27/129

Abstract: A metal oxide sensor is provided on a semiconductor substrate to provide on-chip sensing of gases. The sensor may include a metal layer that may have pores formed by lithography to be of a certain width. The top metal layer may be oxidized resulting in a narrowing of the pores. Another metal layer may be formed over the oxidized layer and electrical contacts may be formed on the metal layer. The contacts may be coupled to a monitoring system that receives electrical signals indicative of gases sensed by the metal oxide sensor.

Abstract translation: 金属氧化物传感器设置在半导体衬底上以提供对气体的片上感测。 传感器可以包括可以具有通过光刻形成的孔以具有一定宽度的金属层。 顶部金属层可能被氧化，导致孔变窄。 可以在氧化层之上形成另一金属层，并且可以在金属层上形成电接触。 触点可以耦合到监测系统，监测系统接收指示由金属氧化物传感器感测的气体的电信号。

公开(公告)号：US20060222852A1

公开(公告)日：2006-10-05

申请号：US11313362

申请日：2005-12-20

Applicant: Valery Dubin ,  Thomas Dory

Inventor： Valery Dubin ,  Thomas Dory

IPC: B32B9/00

CPC classification number: H01L23/373 ,  B82Y10/00 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01037 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  Y10S977/732 ,  Y10S977/744 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T428/30

Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

Abstract translation: 根据本发明的一个方面，提供一种构造电子组件的方法。 在其上集成形成的半导体晶片的背面上形成金属层。 然后，在金属层上形成多孔层。 在孔的底部的多孔层的阻挡层变薄。 然后，催化剂沉积在孔的底部。 然后在孔中生长碳纳米管。 然后在多孔层和碳纳米管上形成另一层金属。 然后将半导体晶片分离成微电子管芯。 将模具结合到半导体衬底，将散热器放置在管芯的顶部，并且由这种组装产生的半导体封装被密封。 在散热器的顶部形成热界面。 然后将散热器放置在热界面的顶部。

公开(公告)号：US20060202342A1

公开(公告)日：2006-09-14

申请号：US11407550

申请日：2006-04-19

Applicant: Tatyana Andreyushchenko ,  Kenneth Cadien ,  Paul Fischer ,  Valery Dubin

Inventor： Tatyana Andreyushchenko ,  Kenneth Cadien ,  Paul Fischer ,  Valery Dubin

IPC: H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76888

Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

公开(公告)号：US20060177946A1

公开(公告)日：2006-08-10

申请号：US11056322

申请日：2005-02-10

Applicant: Valery Dubin

Inventor： Valery Dubin

IPC: H01L21/00 ,  H01L21/4763

CPC classification number: H01L51/0049 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/025 ,  H01L51/0093 ,  Y10S977/788

Abstract: Numerous embodiments of a method to assemble nano-materials on a platform are described. In one embodiment, a nano-material is functionalized with a first bondable group. The functionalized nano-material is disposed on an assembly platform having an electrode to form a first layer. Additional layers of the nano-material may be formed above the first layer to form a semiconductor device. In one embodiment, the nano-material may be a carbon nanotube.

公开(公告)号：US20060160342A1

公开(公告)日：2006-07-20

申请号：US11037860

申请日：2005-01-18

Applicant: Mark Doczy ,  Lawrence Wong ,  Valery Dubin ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau

Inventor： Mark Doczy ,  Lawrence Wong ,  Valery Dubin ,  Justin Brask ,  Jack Kavalieros ,  Suman Datta ,  Matthew Metz ,  Robert Chau

IPC: H01L21/3205

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

Abstract translation: 互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。 在一个实施例中，图案化栅极结构可以由多晶硅形成。 可以使用催化金属通过表面活化来填充沟槽，然后通过化学沉积种子层，然后从下向上超超融合填充来填充沟槽。

公开(公告)号：US20060071340A1

公开(公告)日：2006-04-06

申请号：US10957117

申请日：2004-09-30

Applicant: Ting Zhong ,  Fay Hua ,  Valery Dubin

Inventor： Ting Zhong ,  Fay Hua ,  Valery Dubin

IPC: H01L23/48

CPC classification number: H01L24/13 ,  C23C18/32 ,  C23C18/34 ,  C23C18/36 ,  H01L21/288 ,  H01L21/563 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76874 ,  H01L23/36 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: Metal alloy barrier layers formed of a group VII metal alloyed with boron (B) and/or phosphorous (P) and an at least one element from glyoxylic acid, such as carbon (C), hydrogen (H), or carbon and hydrogen (CH) formed by electoless plating are described. These barrier layers may be used as a barrier layer over copper bumps that are soldered to a tin-based solder in a die package. Such barrier layers may also be used as barrier layer liners within trenches in which copper interconnects or vias are formed and as capping layers over copper interconnects or vias to prevent the electromigration of copper.

Abstract translation: 由与硼（B）和/或磷（P）合金化的第Ⅶ族金属形成的金属合金阻挡层和来自乙醛酸如碳（C），氢（H）或碳和氢的至少一种元素 CH）由无电镀形成。 这些阻挡层可以用作在芯片封装中焊接到锡基焊料的铜凸块上的阻挡层。 这样的阻挡层也可以用作在其中形成铜互连或通孔的沟槽内的阻挡层衬垫，以及作为铜互连或通孔上的覆盖层以防止铜的电迁移。