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公开(公告)号:CN107946280A
公开(公告)日:2018-04-20
申请号:CN201710477486.1
申请日:2017-06-16
Applicant: 日月光半导体制造股份有限公司
IPC: H01L23/528
CPC classification number: H01L24/83 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L2224/13017 , H01L2224/13109 , H01L2224/13111 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16147 , H01L2224/29109 , H01L2224/29111 , H01L2224/29118 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/32147 , H01L2224/81385 , H01L2224/81898 , H01L2224/83139 , H01L2224/83895 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2924/10253 , H01L2924/10271 , H01L2924/3511 , H01L2224/81 , H01L23/5283
Abstract: 本发明提供一种一半导体封装,其包括:一第一基板,其包括自该第一基板之一表面延伸之一第一互连结构,该第一互连结构包括一第一尺寸之颗粒;一第二基板,其包括一第二互连结构,该第二互连结构包括一第二尺寸之颗粒;及一第三互连结构,其系设置于该第一互连结构与该第二互连结构之间,该第三互连结构包括一第三尺寸之颗粒;一第一侧壁,其相对于一参考平面倾斜一第一角度;及一第二侧壁,其相对于该参考平面倾斜一第二角度,其中该第一角度相异于该第二角度,该第一侧壁系设置于该第一基板与该第二侧壁之间,且该第三尺寸小于该第一尺寸与该第二尺寸两者。
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公开(公告)号:CN107134430A
公开(公告)日:2017-09-05
申请号:CN201710234357.X
申请日:2017-02-28
Applicant: 商升特公司
IPC: H01L21/768 , H01L23/538 , H01L27/02
CPC classification number: H01L25/50 , H01L21/304 , H01L21/561 , H01L21/76898 , H01L21/78 , H01L23/295 , H01L23/3121 , H01L23/3171 , H01L23/49575 , H01L23/60 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/85 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L27/0255 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05548 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/0558 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/08146 , H01L2224/08148 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/13025 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16146 , H01L2224/16147 , H01L2224/16227 , H01L2224/16245 , H01L2224/17181 , H01L2224/2929 , H01L2224/32145 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/4847 , H01L2224/73253 , H01L2224/73257 , H01L2224/80203 , H01L2224/8082 , H01L2224/80895 , H01L2224/81203 , H01L2224/81815 , H01L2224/8182 , H01L2224/85203 , H01L2224/85205 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10322 , H01L2924/10324 , H01L2924/10329 , H01L2924/1033 , H01L2924/10335 , H01L2924/1203 , H01L2924/141 , H01L2924/143 , H01L2924/1433 , H01L2924/1434 , H01L2924/1461 , H01L2924/01082 , H01L2224/11 , H01L2224/03 , H01L2224/81 , H01L2224/80 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L23/5384 , H01L23/5386 , H01L27/0292 , H01L27/0296
Abstract: 本发明公开堆叠半导体管芯以用于系统级ESD保护的半导体装置和方法。一种半导体装置具有包括第一保护电路的第一半导体管芯。包括第二保护电路的第二半导体管芯被设置在第一半导体管芯上面。移除第一半导体管芯和第二半导体管芯的一部分以减小管芯厚度。形成互连结构以共同地连接第一保护电路和第二保护电路。使入射到互连结构的瞬变情况共同地通过第一保护电路和第二保护电路放电。具有保护电路的任何数目半导体管芯可以被堆叠并经由互连结构而互连以增加ESD电流放电能力。可以通过将第一半导体晶片设置在第二半导体晶片上面然后将晶片单片化来实现管芯堆叠。替换地,使用管芯到晶片或管芯到管芯组装。
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公开(公告)号:CN104733327A
公开(公告)日:2015-06-24
申请号:CN201410778317.8
申请日:2014-12-15
CPC classification number: H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014
Abstract: 本发明涉及用于对准微电子组件的方法。根据本发明,第一微电子组件到第二微电子组件的接收表面的对准通过由毛细作用力产生的自对准,结合静电对准,来实现。后者通过沿对应组件的周边提供至少一个第一电导线以及沿第二组件的接收表面上的要放置所述组件的位置的周边提供至少一个第二电导体来实现。由导线围绕的接触区覆盖有润湿层。电导线可被嵌入在沿所述周边行进以创建可润湿能力对比的抗湿材料带中。可润湿能力对比在维持接触区之间的一滴对准液体方面是可操纵的,以通过毛细作用力来获得自对准。通过对导线施加适当的电荷,实现了静电自对准,它改进了通过毛细作用力获得的对准并在液体的蒸发期间维持所述对准。
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公开(公告)号:CN102623440B
公开(公告)日:2015-05-20
申请号:CN201110460504.8
申请日:2011-12-31
Applicant: 富士通株式会社
Inventor: 赤松俊也
IPC: H01L25/00 , H01L25/065 , H01L23/48 , H01L23/498 , H01L21/60 , H01L21/50
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/50 , H01L29/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/11002 , H01L2224/1147 , H01L2224/13006 , H01L2224/13024 , H01L2224/13025 , H01L2224/13027 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/14181 , H01L2224/16141 , H01L2224/16147 , H01L2224/16148 , H01L2224/16238 , H01L2224/1624 , H01L2224/1703 , H01L2224/17051 , H01L2224/17181 , H01L2224/45144 , H01L2224/48095 , H01L2224/48227 , H01L2224/48599 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/81136 , H01L2224/8114 , H01L2224/81192 , H01L2224/81193 , H01L2224/81815 , H01L2224/81986 , H01L2224/83102 , H01L2224/9201 , H01L2224/94 , H01L2224/96 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06575 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15159 , H01L2924/15321 , H01L2924/15787 , H01L2924/1579 , H01L2924/351 , H05K1/18 , H05K1/181 , H05K2201/09063 , H05K2201/1053 , H05K2201/10545 , H05K2201/10674 , H01L2224/13099 , H01L2224/11 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/81 , H01L2924/00012 , H01L2224/48624 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 公开了一种半导体装置、制造半导体装置的方法和电子装置。该半导体装置包括半导体元件和电子元件。半导体元件具有第一突出电极,并且电子元件具有第二突出电极。基底被布置在半导体元件与电子元件之间。基底具有通孔,第一和第二突出电极配合在通孔中。第一和第二突出电极在基底的通孔内连接到一起。基底具有绝缘膜,绝缘膜覆盖第一通孔的侧壁并且暴露在第一通孔内,并且第一突出电极的直径和第二突出电极的直径小于第一通孔的直径。
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公开(公告)号:CN102047418B
公开(公告)日:2013-10-16
申请号:CN200980119189.3
申请日:2009-04-22
Applicant: 美光科技公司
Inventor: 戴维·普拉特
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/1147 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/16147 , H01L2224/16235 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2225/06513 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
Abstract: 包括裸片的裸片堆叠和形成所述裸片堆叠的方法提供用于在多种电子系统中使用的结构,其中所述裸片具有带凹导电槽的环状通孔。在一实施例中,裸片堆叠包括在裸片的顶部上的导电柱,所述导电柱被插入到另一裸片的所述凹导电槽中。
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公开(公告)号:CN103187380A
公开(公告)日:2013-07-03
申请号:CN201210593062.9
申请日:2012-12-31
Applicant: 马克西姆综合产品公司
IPC: H01L23/488 , H01L21/60
CPC classification number: H01L24/81 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68381 , H01L2224/02313 , H01L2224/02331 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/03828 , H01L2224/0401 , H01L2224/05025 , H01L2224/0508 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/11002 , H01L2224/11334 , H01L2224/11849 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13111 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/81 , H01L2224/81191 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/181 , H01L2924/01047 , H01L2924/01029 , H01L2924/01082 , H01L2924/00014 , H01L2924/01013 , H01L2224/11 , H01L2224/02 , H01L2224/03 , H01L2924/00
Abstract: 半导体装置描述为包括仅部分地穿入基板延伸的通路。穿基板通路(TSV)向形成于基板中的电子器件提供电互连。在实施例中,通过首先用粘合材料将半导体晶圆粘合到载体晶圆来制造半导体装置。所述半导体晶圆包括布置在晶圆内(例如,在晶圆的第一表面和第二表面之间)的蚀刻阻止部。穿入晶圆形成一个或多个通路。所述通路从第二表面延伸到蚀刻阻止部。
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公开(公告)号:CN103026484A
公开(公告)日:2013-04-03
申请号:CN201280002155.8
申请日:2012-01-11
Applicant: 松下电器产业株式会社
IPC: H01L21/82 , H01L21/822 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00 , H01L27/04
CPC classification number: H01L23/49527 , H01L22/22 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L27/0688 , H01L2224/13009 , H01L2224/13147 , H01L2224/16147 , H01L2224/16225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/3511 , H03K19/00392 , H01L2924/00014 , H01L2924/00
Abstract: 本发明提供一种三维集成电路。芯片重叠于再布线构件上。接合构件和冗余接合构件形成于芯片上,并对芯片和再布线构件之间进行电连接。在芯片和再布线部件分别形成有冗余救济电路,在连接部件之一产生缺陷的情况下,使冗余接合构件之一代替包含缺陷的接合构件而在芯片和在布线构件之间传递信号。在再布线构件和芯片之间的间隔比规定阈值大的区域比其他的区域,在多个接合构件中通过冗余救济电路能够以冗余接合构件进行代替的接合构件的比例高。
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公开(公告)号:CN101320702A
公开(公告)日:2008-12-10
申请号:CN200810110005.4
申请日:2008-06-02
Applicant: 株式会社瑞萨科技
IPC: H01L21/60 , H01L23/485
CPC classification number: H01L21/76898 , H01L21/6835 , H01L24/05 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/05025 , H01L2224/05553 , H01L2224/0557 , H01L2224/05572 , H01L2224/1134 , H01L2224/13025 , H01L2224/13099 , H01L2224/16147 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/90 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00013 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/14 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
Abstract: 本发明提供一种半导体器件及其制造方法,可以提高具有三维地层叠的多个半导体芯片的半导体器件的制造成品率。形成有从半导体基板(1)的第2面(1b)到达焊盘(3)的贯通电极(17)。贯通电极(17)的内部的贯通空间是由第1孔(7)以及孔径小于第1孔(7)的第2孔(11)构成的。从半导体基板(1)的第2面(1b)贯通半导体基板(1)直到层间绝缘膜(2)的途中地形成有第1孔(7)。另外,形成有从第1孔(7)的底部贯通层间绝缘膜(2)到达焊盘(3)的第2孔(11)。此时,形成在半导体基板(1)的第1面(1a)上的层间绝缘膜(2)反映第1孔(7)的底面与半导体基板(1)的第1面(1a)造成的台阶而成为台阶形状。即,存在于第1孔(7)的底面与焊盘(3)间的层间绝缘膜(2)的膜厚比其他位置的层间绝缘膜(2)的膜厚薄。
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公开(公告)号:CN104733327B
公开(公告)日:2018-11-23
申请号:CN201410778317.8
申请日:2014-12-15
CPC classification number: H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014
Abstract: 本发明涉及用于对准微电子组件的方法。根据本发明,第一微电子组件到第二微电子组件的接收表面的对准通过由毛细作用力产生的自对准,结合静电对准,来实现。后者通过沿对应组件的周边提供至少一个第一电导线以及沿第二组件的接收表面上的要放置所述组件的位置的周边提供至少一个第二电导体来实现。由导线围绕的接触区覆盖有润湿层。电导线可被嵌入在沿所述周边行进以创建可润湿能力对比的抗湿材料带中。可润湿能力对比在维持接触区之间的一滴对准液体方面是可操纵的,以通过毛细作用力来获得自对准。通过对导线施加适当的电荷,实现了静电自对准,它改进了通过毛细作用力获得的对准并在液体的蒸发期间维持所述对准。
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公开(公告)号:CN103985683B
公开(公告)日:2017-04-12
申请号:CN201410042921.4
申请日:2014-01-29
Applicant: 精材科技股份有限公司
IPC: H01L23/488
CPC classification number: H01L23/481 , H01L23/525 , H01L24/05 , H01L24/16 , H01L29/0657 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05548 , H01L2224/05558 , H01L2224/05572 , H01L2224/131 , H01L2224/16 , H01L2224/16146 , H01L2224/16147 , H01L2224/16237 , H01L2224/48091 , H01L2224/48151 , H01L2224/73207 , H01L2924/10156 , H01L2924/13091 , H01L2924/1461 , H01L2924/15788 , H01L2924/00014 , H01L2924/00 , H01L2924/014
Abstract: 本发明提供一种晶片封装体,其包括:一半导体基底,具有一第一表面及一第二表面;一第一凹陷,自该第一表面朝该第二表面延伸;一第二凹陷,自该第一凹陷的一底部朝该第二表面延伸,其中该第一凹陷的一侧壁及该底部与该第二凹陷的一第二侧壁及一第二底部共同形成该半导体基底的一外侧表面;一导线层,设置于该第一表面上,且延伸进入该第一凹陷及/或该第二凹陷;一绝缘层,位于该导线层与该半导体基底之间;一晶片,设置于该第一表面上;以及一导电结构,设置于该晶片与该第一表面之间。本发明不仅有助于晶片封装体的缩小化,还可提升导线层的可靠度。
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