公开(公告)号：US20190066807A1

公开(公告)日：2019-02-28

申请号：US15691840

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Rainer Bonitz

IPC: G11C16/34 ,  G11C16/08

CPC classification number: G11C16/3418 ,  G11C5/144 ,  G11C14/0063 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: Methods of operating apparatus, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of an array of volatile memory cells of the apparatus, determining if a power loss to the apparatus is indicated, and, if a power loss to the apparatus is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells of the apparatus responsive to the information indicative of the data value stored in the particular memory cell. A resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

公开(公告)号：US20170330628A1

公开(公告)日：2017-11-16

申请号：US15294948

申请日：2016-10-17

Applicant: SK hynix Inc.

Inventor： Sung-Lae OH ,  Jin-Ho KIM ,  Sang-Hyun SUNG

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24 ,  G11C14/00

CPC classification number: G11C16/16 ,  G11C8/12 ,  G11C14/0063 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24

Abstract: A nonvolatile memory device includes a memory block including a plurality of cell strings each of which includes memory cells electrically coupled with word lines stacked over a substrate; a plurality of sub common sources electrically coupled to one ends of the cell strings; and a plurality of bit lines electrically coupled to the other ends of the cell strings, wherein the memory block includes sub blocks respectively corresponding to the sub common sources, and cell strings electrically coupled to the same bit line among the cell strings are included in the same sub block.

公开(公告)号：US20170310341A1

公开(公告)日：2017-10-26

申请号：US15412353

申请日：2017-01-23

Applicant: SK Hynix Inc.

Inventor： Wei-Hao Yuan ,  Johnson Yen ,  ChunHok Ho

IPC: H03M13/11 ,  G11C29/52 ,  G11C14/00 ,  G11C11/56 ,  G06F3/06 ,  H03M13/00

CPC classification number: H03M13/1105 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0635 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2003/0691 ,  G11C7/1006 ,  G11C7/1084 ,  G11C11/5628 ,  G11C11/5642 ,  G11C14/0018 ,  G11C14/0063 ,  G11C16/10 ,  G11C29/52 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  H03M13/1102 ,  H03M13/611

Abstract: Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.

公开(公告)号：US20170294225A1

公开(公告)日：2017-10-12

申请号：US15630614

申请日：2017-06-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C11/412 ,  H01L29/423 ,  G11C14/00 ,  H01L29/788 ,  H01L23/522 ,  H01L27/11 ,  H01L29/08 ,  H01L29/51

CPC classification number: G11C11/41 ,  G11C11/4125 ,  G11C14/0054 ,  G11C14/0063 ,  G11C16/0416 ,  H01L23/5226 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

公开(公告)号：US20170287559A1

公开(公告)日：2017-10-05

申请号：US15466771

申请日：2017-03-22

Applicant: Chengdu Monolithic Power Systems Co., Ltd.

Inventor： Da Chen ,  Eric Braun

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L29/788

CPC classification number: G11C14/0063 ,  G11C7/065 ,  G11C7/067 ,  G11C11/412 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  H01L29/7886

Abstract: A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.

公开(公告)号：US09666236B2

公开(公告)日：2017-05-30

申请号：US15083847

申请日：2016-03-29

Applicant: SK hynix Inc.

Inventor： Hyun-Bae Lee

IPC: G11C5/02 ,  H01L25/065 ,  H01L23/00 ,  G11C14/00 ,  G11C5/14 ,  G11C16/04

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/147 ,  G11C7/1084 ,  G11C14/0063 ,  G11C16/0483 ,  G11C2207/105 ,  H01L24/09 ,  H01L25/0657 ,  H01L2224/0912 ,  H01L2225/06506 ,  H01L2225/0651

Abstract: A multi-chip package (MCP) includes semiconductor chips integrated therein. Each semiconductor chip includes: pad groups which extend in a first direction and are arranged in a second direction, and each of which includes a first metal line and a second metal line that are stacked in a third direction with an interlayer dielectric layer interposed therebetween; receivers which one-to-one correspond to the respective pad groups, and each of which includes a first input terminal coupled with the first metal line of a corresponding pad group, and an output terminal coupled with the second metal line of the corresponding pad group; and selectors, each of which selects one of a feedback signal transferred from the output terminal of a corresponding receiver and a reference voltage, and provides the selected one to a second input terminal of the corresponding receiver, in response to a chip select signal.

公开(公告)号：US09646694B2

公开(公告)日：2017-05-09

申请号：US14886663

申请日：2015-10-19

Applicant: Cypress Semiconductor Corporation

Inventor： Joseph S. Tandingan ,  Jayant Ashokkumar ,  David Still ,  Jesse J. Siman

IPC: G11C14/00 ,  G11C16/04

CPC classification number: G11C11/419 ,  G11C14/0063 ,  G11C16/0466

Abstract: A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

公开(公告)号：US09437254B2

公开(公告)日：2016-09-06

申请号：US14728900

申请日：2015-06-02

Applicant: Micron Technology, Inc.

Inventor： Federico Pio

IPC: G11C16/04 ,  G11C5/14 ,  G11C16/26 ,  G11C16/12 ,  G06F21/60 ,  G11C16/06 ,  G11C16/30 ,  G11C7/22 ,  G11C7/10 ,  G11C14/00 ,  G06F12/02 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

Abstract: A method is provided for using a multi-level cell memory device. The method includes writing first data to a first portion of a memory array using a first number of state levels for memory cells of the first portion of the memory array. The method further includes re-writing second data to a second portion of the memory array using a second number of state levels for memory cells of the second portion of the memory array. The second number is different from the first number.

Abstract translation: 提供了一种使用多级单元存储器件的方法。 该方法包括使用存储器阵列的第一部分的存储器单元的第一数量的状态级将第一数据写入存储器阵列的第一部分。 该方法还包括使用存储器阵列的第二部分的存储器单元的第二数量的状态级将第二数据重写到存储器阵列的第二部分。 第二个数字与第一个数字不同。

公开(公告)号：US09378821B1

公开(公告)日：2016-06-28

申请号：US13791758

申请日：2013-03-08

Applicant: Cypress Semiconductor Corporation

Inventor： Venkatraman Prabhakar ,  Long Hinh ,  Kaveh Shakeri ,  Sarath C. Puthenthermadam

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16

CPC classification number: G11C16/12 ,  G11C14/0063 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14

Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.

Abstract translation: 描述用于编程和擦除硅氧化物 - 氮化物 - 氧化物 - 硅（SONOS）存储器单元的脉冲信号的脉冲整形的装置和方法。 在一种方法中，脉冲信号的脉冲形状被控制为包括用于编程或擦除SONOS存储器单元的四个或更多个相位。 执行写周期以用具有四个或多个相位的脉冲信号来编程或擦除SONOS存储器。

公开(公告)号：US09350334B2

公开(公告)日：2016-05-24

申请号：US14510310

申请日：2014-10-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K3/00 ,  H03K3/356 ,  G11C7/04 ,  G11C14/00 ,  H01L27/105 ,  H01L27/12 ,  H03K3/037 ,  H03K3/286 ,  G11C16/04 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC classification number: H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.