公开(公告)号：US20180268892A1

公开(公告)日：2018-09-20

申请号：US15709674

申请日：2017-09-20

Applicant: SK hynix Inc.

Inventor： Jeong-Hwan KIM ,  Jin-Ho KIM ,  Sang-Hyun SUNG

IPC: G11C11/408 ,  G11C8/10 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a memory cell array and a row decoder disposed in a first direction over a substrate and a plurality of coupling lines for electrically coupling the memory cell array and the row decoder. Each of the coupling lines includes a first conductive line disposed in the first direction; a second conductive line disposed parallel to the first conductive line; and a pad coupling the first conductive line and the second conductive line, and coupled to the memory cell array or the row decoder through a contact plug. The coupling lines are routed from both sides of the pad in the first direction.

公开(公告)号：US20180337054A1

公开(公告)日：2018-11-22

申请号：US15792965

申请日：2017-10-25

Applicant: SK hynix Inc.

Inventor： Sang-Hyun SUNG ,  Jeong-Hwan KIM ,  Jin-Ho KIM

IPC: H01L21/28 ,  H01L49/02 ,  H01L27/11 ,  H01L29/423 ,  G11C5/06 ,  H01L27/11519 ,  G11C7/18

CPC classification number: H01L21/28273 ,  G11C5/063 ,  G11C7/18 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/75 ,  H01L28/87 ,  H01L28/91 ,  H01L29/42324

Abstract: A semiconductor memory device includes a semiconductor layer including a memory cell region; a memory cell array including a plurality of first gate electrode layers stacked over the semiconductor layer, and disposed in the memory cell region; and a capacitor circuit disposed over the semiconductor layer outside the memory cell region. The capacitor circuit includes a plurality of gate structural bodies each including second gate electrode layers stacked over the semiconductor layer, and arranged along a first direction; a plurality of electrodes disposed between the gate structural bodies; and dielectric layers interposed between the gate structural bodies and the electrodes.

公开(公告)号：US20200020712A1

公开(公告)日：2020-01-16

申请号：US16199356

申请日：2018-11-26

Applicant: SK hynix Inc.

Inventor： Jin-Ho KIM ,  Young-Ki KIM ,  Jeong-Hwan KIM ,  Sang-Hyun SUNG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a substrate including a cell region and a slimming region; a logic structure disposed over the substrate, the logic structure including logic circuit elements and bottom wiring lines electrically coupled to the logic circuit elements; a source plate disposed over the logic structure; a memory structure including a plurality of memory cells and a plurality of gate electrode layers, wherein the plurality of memory cells are disposed over the source plate of the cell region and a plurality of gate electrode layers are stacked over the source plate of the cell region and the slimming region to be separated from one another and are coupled to the plurality of memory cells; and a first slit cutting the source plate at a boundary between the cell region and the slimming region, wherein the source plate of the slimming region is floated regardless an operation of the memory cells and the logic circuit elements.

公开(公告)号：US20170330628A1

公开(公告)日：2017-11-16

申请号：US15294948

申请日：2016-10-17

Applicant: SK hynix Inc.

Inventor： Sung-Lae OH ,  Jin-Ho KIM ,  Sang-Hyun SUNG

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24 ,  G11C14/00

CPC classification number: G11C16/16 ,  G11C8/12 ,  G11C14/0063 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24

Abstract: A nonvolatile memory device includes a memory block including a plurality of cell strings each of which includes memory cells electrically coupled with word lines stacked over a substrate; a plurality of sub common sources electrically coupled to one ends of the cell strings; and a plurality of bit lines electrically coupled to the other ends of the cell strings, wherein the memory block includes sub blocks respectively corresponding to the sub common sources, and cell strings electrically coupled to the same bit line among the cell strings are included in the same sub block.