公开(公告)号：US09876012B2

公开(公告)日：2018-01-23

申请号：US14954854

申请日：2015-11-30

申请人： INTERSIL AMERICAS LLC

发明人： Francois Hebert

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/40 ,  H01L21/265 ,  H01L23/535 ,  H01L23/62 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H02M7/00

CPC分类号： H01L27/088 ,  H01L21/26513 ,  H01L21/823437 ,  H01L21/823487 ,  H01L23/535 ,  H01L23/62 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/30107 ,  H01L2924/3025 ,  H02M7/003 ,  H01L2924/00

摘要： A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

公开(公告)号：US20170373055A1

公开(公告)日：2017-12-28

申请号：US15700679

申请日：2017-09-11

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L27/06 ,  H02M3/155 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/8234 ,  H01L21/28 ,  H02M7/00 ,  H01L29/417 ,  H01L29/10 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

公开(公告)号：US09837340B2

公开(公告)日：2017-12-05

申请号：US15195310

申请日：2016-06-28

申请人： Intel Corporation

发明人： Jiamiao Tang ,  Henry Xu ,  Shinichi Sakamoto

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/50 ,  H01L25/18 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L23/49811 ,  H01L21/50 ,  H01L21/56 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/24 ,  H01L24/25 ,  H01L24/43 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2021/60007 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/435 ,  H01L2224/43985 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85138 ,  H01L2224/85815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/48

摘要： Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

公开(公告)号：US09824944B2

公开(公告)日：2017-11-21

申请号：US15280618

申请日：2016-09-29

申请人： Renesas Electronics Corporation

发明人： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

摘要： A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

公开(公告)号：US09806680B2

公开(公告)日：2017-10-31

申请号：US15265047

申请日：2016-09-14

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Alan William Ake ,  David C. Dening

IPC分类号： H03F3/14 ,  H03F3/195 ,  H03F1/30 ,  H01L23/66 ,  H03F1/32 ,  H03F3/191 ,  H03F3/193 ,  H03F3/21 ,  H03F3/24 ,  H03F3/343 ,  H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H04B1/44 ,  H03G3/30 ,  H03F1/02 ,  H03F3/187

CPC分类号： H03F3/195 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/665 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1203 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03F1/0261 ,  H03F1/302 ,  H03F1/32 ,  H03F1/3205 ,  H03F3/187 ,  H03F3/191 ,  H03F3/193 ,  H03F3/211 ,  H03F3/245 ,  H03F3/3435 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/93 ,  H03G3/30 ,  H04B1/44 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

摘要： Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin.

公开(公告)号：US09793265B2

公开(公告)日：2017-10-17

申请号：US15265940

申请日：2016-09-15

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L27/06 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L29/78 ,  H02M7/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H02M3/155 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

公开(公告)号：US09761948B2

公开(公告)日：2017-09-12

申请号：US14733311

申请日：2015-06-08

申请人： FRACTUS, S.A

发明人： Jordi Soler Castany ,  Jaume Anguera Pros ,  Carles Puente Baliarda ,  Carmen Borja Borau

IPC分类号： H01Q1/00 ,  H01Q9/04 ,  H01L23/66 ,  H01L25/16 ,  H01Q1/22 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/40 ,  H01Q9/42 ,  H01Q13/10 ,  H01L23/00

CPC分类号： H01Q9/045 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/165 ,  H01L2223/6677 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/207 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01Q1/22 ,  H01Q1/2283 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/30 ,  H01Q9/40 ,  H01Q9/42 ,  H01Q13/10 ,  H01L2924/00

摘要： The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

公开(公告)号：US20170256483A1

公开(公告)日：2017-09-07

申请号：US15245924

申请日：2016-08-24

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hiroshi MATSUYAMA

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18

CPC分类号： H01L23/49541 ,  H01L23/15 ,  H01L23/3672 ,  H01L23/3731 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49838 ,  H01L23/49844 ,  H01L24/01 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/29101 ,  H01L2224/32157 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

摘要： A semiconductor device includes a first conductive layer with first and second sections separated in a first direction. A first chip is on the first section and has a first, second and third electrodes. A second chip is on the second section and has a fourth and fifth electrode. A second conductive layer is between the sections of the first conductive layer in the first direction. The second conductive layer has a first connected section to which the second electrode is connected, a second connected section to which to the fifth electrode is connected, and a first clearance portion between the first and second connected sections in the first direction. A third conductive layer is spaced from the first conductive layer and the second conductive layer and is connected to the third electrode.

公开(公告)号：US09754871B2

公开(公告)日：2017-09-05

申请号：US14798484

申请日：2015-07-14

申请人： Delta Electronics (Shanghai) Co., Ltd.

发明人： Zeng Li ,  Shou-Yu Hong ,  Jian-Hong Zeng

IPC分类号： H01L23/522 ,  H01L27/088 ,  H01L23/495 ,  H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/66 ,  G11B5/4873 ,  H01L21/568 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L27/088 ,  H01L29/92 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors. The semiconductor switch unit includes a plurality of common electrodes, each common electrode connects the source electrode of one sub micro-switch element in the first semiconductor switch element with the drain of one sub micro-switch element in the second semiconductor switch element and is disposed adjacent to at least one drain electrode from the first semiconductor switch element or one source electrode from the second semiconductor switch element.

公开(公告)号：US09741702B2

公开(公告)日：2017-08-22

申请号：US14950411

申请日：2015-11-24

申请人： Transphorm Inc.

发明人： Yifeng Wu

IPC分类号： H01L25/00 ,  H01L25/07 ,  H05K1/02 ,  H03K17/16 ,  H01L23/12 ,  H01L23/367 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78 ,  H01L23/498 ,  H01L25/11 ,  H05K1/16 ,  H01L23/552 ,  H01L23/64 ,  H01L25/16

CPC分类号： H01L25/50 ,  H01L23/12 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/552 ,  H01L23/642 ,  H01L25/074 ,  H01L25/117 ,  H01L25/16 ,  H01L25/165 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/7827 ,  H01L2224/48091 ,  H01L2924/13055 ,  H01L2924/30107 ,  H03K17/164 ,  H03K2217/0045 ,  H05K1/0218 ,  H05K1/0263 ,  H05K1/162 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10545 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.