公开(公告)号：US20240063159A1

公开(公告)日：2024-02-22

申请号：US17891949

申请日：2022-08-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： An-Hsuan HSU ,  Chin-Li KAO

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/35121 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/08221 ,  H01L2224/80098 ,  H01L2224/80895 ,  H01L2224/83098 ,  H01L2224/05541 ,  H01L2224/05556 ,  H01L2224/08503 ,  H01L2224/05647 ,  H01L2224/05605 ,  H01L2224/80815

Abstract: A package structure is disclosed. The package structure includes a substrate including a conductive element and a plurality of wires having a surface area through which heat of the conductive element can be dissipated, lowering a bonding temperature of the conductive element. The package structure also includes a conductive layer disposed between the conductive element of the substrate and the plurality of wires. The conductive contact layer attaches the plurality of wires over the conductive element.

公开(公告)号：US11664335B2

公开(公告)日：2023-05-30

申请号：US15358038

申请日：2016-11-21

Applicant: Semikron Elektronik GmbH & Co., KG

Inventor： Wolfgang-Michael Schulz

IPC: H01L23/00 ,  H01L23/488

CPC classification number: H01L24/05 ,  H01L23/488 ,  H01L24/03 ,  H01L24/08 ,  H01L24/48 ,  H01L24/85 ,  H01L24/45 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03462 ,  H01L2224/03823 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/0508 ,  H01L2224/0516 ,  H01L2224/05023 ,  H01L2224/0558 ,  H01L2224/0566 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05583 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/05684 ,  H01L2224/08503 ,  H01L2224/45005 ,  H01L2224/45015 ,  H01L2224/4554 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48247 ,  H01L2224/48506 ,  H01L2224/48507 ,  H01L2224/48855 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/2076 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05179 ,  H01L2924/00014 ,  H01L2224/05172 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00014 ,  H01L2224/0516 ,  H01L2924/00014 ,  H01L2224/05118 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/01074 ,  H01L2224/05186 ,  H01L2924/01022 ,  H01L2224/45005 ,  H01L2924/2076 ,  H01L2224/45147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/43848 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/01014

Abstract: A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

公开(公告)号：US20180047689A1

公开(公告)日：2018-02-15

申请号：US15555434

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Fay HUA

IPC: H01L23/00

CPC classification number: H01L24/13 ,  B23K35/00 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/08503 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/206 ,  H01L2924/3512 ,  H01L2924/3651 ,  H01L2924/0103 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01013

Abstract: Embodiments of the invention include a semiconductor device and methods of forming the semiconductor device. In an embodiment the semiconductor device comprises a semiconductor die with one or more die contacts. Embodiments include a reflown solder bump on one or more of the die contacts. In an embodiment, an intermetallic compound (IMC) barrier layer is formed at the interface between the solder bump and the die contact. In an embodiment, the IMC barrier layer is a CuZn IMC and/or a Cu5Zn8 IMC.

公开(公告)号：US20130140685A1

公开(公告)日：2013-06-06

申请号：US13309163

申请日：2011-12-01

Applicant: Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L23/495 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/00

Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Abstract translation: 电子设备包括载体，附着到载体的半导体衬底以及设置在半导体衬底和载体之间的层系统。 层系统包括设置在半导体衬底上的电接触层。 功能层设置在电接触层上。 粘附层设置在功能层上。 在粘合层和载体之间设置焊料层。

公开(公告)号：US20130037940A1

公开(公告)日：2013-02-14

申请号：US13417031

申请日：2012-03-09

Applicant: Chih CHEN ,  King-Ning TU ,  Hsiang-Yao HSIAO

Inventor： Chih CHEN ,  King-Ning TU ,  Hsiang-Yao HSIAO

IPC: H01L23/498 ,  H01L21/60

CPC classification number: C23C28/021 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/08503 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: The present invention relates to a method for inhibiting growth of intermetallic compounds, comprising the steps of: (i) preparing a substrate element including a substrate on which at least one layer of metal pad is deposited, wherein at least one thin layer of solder is deposited onto the layer of metal pad, and then carry out reflowing process; and (ii) further depositing a bump of solder with an appropriate thickness on the substrate element, characterized in that a thin intermetallic compound is formed by the reaction of the thin solder layer and the metal in the metal pad after appropriate heat treatment of the thin solder layer. In the present invention, the formation of a thin intermetallic compound is able to slow the growth of the intermetallic compound and to prevent the transformation of the intermetallic compounds.

Abstract translation: 本发明涉及一种抑制金属间化合物生长的方法，其特征在于包括以下步骤：（i）制备包含基材的基材，其上至少沉积有一层金属垫，其中至少一层焊料薄层为 沉积在金属垫层上，然后进行回流处理; 以及（ii）在衬底元件上进一步沉积具有适当厚度的焊料凸点，其特征在于，通过所述薄焊料层与所述金属焊盘中的所述金属的反应形成薄的金属间化合物， 焊锡层。 在本发明中，形成薄的金属间化合物能够减缓金属间化合物的生长并防止金属间化合物的转变。

公开(公告)号：US08299612B2

公开(公告)日：2012-10-30

申请号：US13232682

申请日：2011-09-14

Applicant: Jeffrey A. West ,  Young-Joon Park

Inventor： Jeffrey A. West ,  Young-Joon Park

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/08503 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ≧25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract translation: 贯穿衬底通孔（TSV）管芯包括多个TSV，其包括外部电介质套管，内部金属芯和包括从TSV管芯出现的侧壁的突出的TSV尖端。 突出的TSV尖端的钝化层位于突出的TSV尖端的侧壁的一部分上。 钝化层从突出的TSV尖端的远端部分不存在，以提供内金属芯的暴露部分。 TSV尖端包括覆盖TSV侧壁的一部分的球茎远端尖端在外电介质套筒的最上表面上方，并且具有比截面面积大25％的最大横截面积 突出的TSV尖端在球茎远端尖端下方。

公开(公告)号：US20120235296A1

公开(公告)日：2012-09-20

申请号：US13232682

申请日：2011-09-14

Applicant: Jeffrey A. West ,  Young-Joon Park

Inventor： Jeffrey A. West ,  Young-Joon Park

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/08503 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ≧25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract translation: 贯穿衬底通孔（TSV）管芯包括多个TSV，其包括外部电介质套管，内部金属芯和包括从TSV管芯出现的侧壁的突出的TSV尖端。 突出的TSV尖端的钝化层位于突出的TSV尖端的侧壁的一部分上。 钝化层从突出的TSV尖端的远端部分不存在，以提供内金属芯的暴露部分。 TSV尖端包括覆盖TSV侧壁的一部分的球茎远端尖端在外电介质套筒的最上表面上方，并且具有比截面面积大25％的最大横截面积 突出的TSV尖端在球茎远端尖端下方。

公开(公告)号：US08039385B1

公开(公告)日：2011-10-18

申请号：US12880629

申请日：2010-09-13

Applicant: Jeffrey A. West ,  Young-Joon Park

Inventor： Jeffrey A. West ,  Young-Joon Park

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/08503 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a portion of the sidewalls of the protruding TSV tips. The passivation layers is absent from a distal portion of the protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends including a first metal layer including a first metal other than solder and a second metal layer including a second metal other than solder that covers the exposed tip portion. The bulbous distal tip ends cover a portion of the TSV sidewalls and are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ≧25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract translation: 贯穿衬底通孔（TSV）管芯包括多个TSV，其包括外部电介质套筒和内部金属芯体，以及突出的TSV端部，其包括从TSV管芯出来的侧壁。 突出的TSV尖端侧面的钝化层位于突出的TSV尖端的侧壁的一部分上。 钝化层不存在于突出的TSV尖端的远端部分，以提供内金属芯的暴露部分。 TSV尖端包括球茎远端尖端，其包括包括除焊料之外的第一金属的第一金属层和包括除了暴露的尖端部分的焊料以外的第二金属的第二金属层。 球茎远侧末端覆盖TSV侧壁的一部分并且在外部电介质套管的最上表面之上，并且与下面突出的TSV尖端的横截面面积相比，具有最大横截面面积比≧25％更大 球茎远端尖端。

公开(公告)号：US20230299029A1

公开(公告)日：2023-09-21

申请号：US18183828

申请日：2023-03-14

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Jeremy Alfred Theil ,  Thomas Workman ,  Cyprian Emeka Uzoh ,  Jesus Perez ,  Pawel Mrozek

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L2224/0801 ,  H01L2224/08111 ,  H01L2224/08503

Abstract: An element and a bonded structure including the element are disclosed. The element can include a non-conductive region having a cavity extending at least partially through a thickness of the non-conductive region from the contact surface, and a contact feature formed in the cavity. The non-conductive region is configured to directly bond to a non-conductive region of a second element. The contact pad of the element is configured to directly bond to a contact pad of the second element. The contact pad can include a first conductive material and a second conductive material. The first conductive material can have a unit cell size greater than a unit cell size of the second conductive material. The first conductive material can be a metal alloying material. The first conductive material can be a metal silicide and the second conductive material can be a metal. A bonded conductive contact can include a conductive material and an alloying element, and an amount of the alloying element can vary through a thickness of the bonded conductive contact.

公开(公告)号：US20190006311A1

公开(公告)日：2019-01-03

申请号：US16126190

申请日：2018-09-10

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Michael Juerss ,  Konrad Roesl ,  Oliver Eichinger ,  Kok Chai Goh ,  Tobias Schmidt

IPC: H01L23/00 ,  H01L29/45 ,  H01L29/43 ,  H01L23/482 ,  H01L23/495

CPC classification number: H01L24/32 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/43 ,  H01L29/45 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/08503 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/00

Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.