公开(公告)号：US09595610B2

公开(公告)日：2017-03-14

申请号：US14723673

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong Kwon ,  Shigenobu Maeda ,  David Seo ,  Jae-Hwan Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785

Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.

Abstract translation: 可以形成MOSFET，其具有改善载流子迁移率的晶格常数的应变诱导失配。 在示例性实施例中，MOSFET包括不会被凹陷步骤破坏的应变诱导晶格常数失配。 在一些实施例中，源/漏图案在没有凹陷步骤的情况下生长，从而避免与凹陷步骤相关的问题。 或者，可以以不暴露应变松弛缓冲层的顶表面的方式执行凹陷处理。 诸如应变松弛缓冲层或器件隔离层的MOSFET器件层不受凹陷步骤的影响，结果可能将应变施加到沟道区而不会影响随后的形成步骤。

公开(公告)号：US09379319B2

公开(公告)日：2016-06-28

申请号：US14444083

申请日：2014-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/02 ,  H01L45/00 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Abstract translation: 提供了非易失性存储晶体管和包括非易失性存储晶体管的器件。 非易失性存储晶体管可以包括沟道元件，对应于沟道元件的栅极电极，沟道元件和栅电极之间的栅极绝缘层，栅极绝缘层和栅电极之间的离子物质移动层，以及源极 以及相对于沟道元件彼此分离的漏极。 根据施加到栅电极的电压，发生离子物质移动层处的离子物质的运动。 阈值电压根据离子物质的运动而变化。 非易失性存储晶体管具有多电平特性。

公开(公告)号：US09306005B2

公开(公告)日：2016-04-05

申请号：US14103079

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-eun Byun ,  Seong-jun Park ,  David Seo ,  Hyun-jae Song ,  Jae-ho Lee ,  Hyun-jong Chung ,  Jin-seong Heo

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/739 ,  H01L29/786 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/1606 ,  H01L29/1087 ,  H01L29/45 ,  H01L29/452 ,  H01L29/456 ,  H01L29/458 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/78618

Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm−3, and a depletion width of less than or equal to 3 nm.

Abstract translation: 根据示例性实施例，电子设备包括：半导体层; 直接接触所述半导体层的期望（和/或备选地预定）区域的石墨烯; 和石墨烯上的金属层。 半导体层的期望（和/或备选地）预定区域包括以下之一：恒定的掺杂密度，等于或小于1019cm-3的掺杂密度以及小于或等于3nm的耗尽宽度 。

公开(公告)号：US09054708B2

公开(公告)日：2015-06-09

申请号：US13737450

申请日：2013-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-wook Kim ,  Seong-jun Park ,  David Seo ,  Young-jun Yun ,  Yung-hee Yvette Lee ,  Chang-seung Lee

IPC: G06F3/041 ,  H03K17/96 ,  B82Y15/00

CPC classification number: H03K17/96 ,  B82Y15/00 ,  H03K17/962

Abstract: A touch sensor using a graphene diode and/or a touch panel including the touch sensor. The touch sensor includes a first sensing electrode configured to sense a touch; a first output line configured to transmit an electrical signal; and a first diode device including a first control terminal connected to the first sensing electrode, a first anode terminal connected to a voltage application unit, and a first cathode terminal connected to the first output line.

Abstract translation: 使用石墨烯二极管的触摸传感器和/或包括触摸传感器的触摸面板。 所述触摸传感器包括被配置为感测触摸的第一感测电极; 配置为发送电信号的第一输出线; 以及第一二极管器件，包括连接到第一感测电极的第一控制端子，连接到电压施加单元的第一阳极端子和连接到第一输出线的第一阴极端子。

公开(公告)号：US09053932B2

公开(公告)日：2015-06-09

申请号：US13917786

申请日：2013-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Wook Lee ,  Hyeon-jin Shin ,  Seong-jun Park ,  Kyung-eun Byun ,  David Seo ,  Hyun-jae Song ,  Yun-sung Woo ,  Jae-ho Lee ,  Hyun-jong Chung ,  Jin-seong Heo

IPC: H01L21/20 ,  H01L21/36 ,  C01B31/04 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L21/02527 ,  H01L21/0242 ,  H01L21/02529 ,  H01L21/02612 ,  H01L21/02656 ,  H01L29/1606

Abstract: A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film.

Abstract translation: 制备石墨烯的方法包括在基板上形成碳化硅薄膜，在碳化硅薄膜上形成金属薄膜，通过加热碳化硅薄膜和金属薄膜，在基板上形成金属复合层和石墨烯 电影。

公开(公告)号：US09768062B1

公开(公告)日：2017-09-19

申请号：US15276748

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  David Seo ,  Kota Oikawa ,  Kim Changhwa ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/785

Abstract: A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

公开(公告)号：US20160268418A1

公开(公告)日：2016-09-15

申请号：US15165372

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  G11C14/00 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

公开(公告)号：US09373685B2

公开(公告)日：2016-06-21

申请号：US14180928

申请日：2014-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-jin Shin ,  Kyung-eun Byun ,  Hyun-jae Song ,  Seong-jun Park ,  David Seo ,  Yun-sung Woo ,  Dong-wook Lee ,  Jae-ho Lee ,  Hyun-jong Chung ,  Jin-seong Heo ,  In-kyeong Yoo

IPC: H01L29/78 ,  H01L29/16 ,  H01L51/00 ,  H01L51/42 ,  H01L51/50 ,  H01L51/05 ,  H01L29/786 ,  H01L31/028 ,  H01L33/34 ,  H01L31/08

CPC classification number: H01L29/1606 ,  H01L29/786 ,  H01L29/78642 ,  H01L29/78684 ,  H01L31/028 ,  H01L31/08 ,  H01L33/34 ,  H01L51/0046 ,  H01L51/0504 ,  H01L51/0558 ,  H01L51/0562 ,  H01L51/0566 ,  H01L51/057 ,  H01L51/428 ,  H01L51/50

Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Abstract translation: 提供了石墨烯装置和包括该石墨烯装置的电子装置。 根据示例性实施例，石墨烯装置包括晶体管，其包括源极，栅极和漏极，载流子移动的有源层以及栅极和有源层之间的石墨烯层。 石墨烯层可以被配置为既用作有源层的电极和晶体管的沟道层。

公开(公告)号：US09306021B2

公开(公告)日：2016-04-05

申请号：US14244223

申请日：2014-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-jong Chung ,  David Seo ,  Seong-jun Park ,  Kyung-eun Byun ,  Hyun-jae Song ,  Hee-jun Yang ,  Jin-seong Heo

IPC: H01L29/02 ,  H01L29/47 ,  H01L21/74 ,  H01L29/778 ,  H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/47 ,  B82Y10/00 ,  H01L21/74 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1606 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7781 ,  H01L29/7839

Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.

Abstract translation: 石墨烯装置包括：具有第一区域和第二区域的半导体衬底; 在第一区域上但不在半导体衬底的第二区域上的石墨烯层; 在所述石墨烯层的第一部分上的第一电极; 在所述石墨烯层的第二部分上的第二电极; 石墨烯层和第二电极之间的绝缘层; 以及在所述半导体衬底的第二区域上的第三电极。 半导体衬底具有由石墨烯层和半导体衬底的结合形成的可调肖特基势垒。

公开(公告)号：US09299789B2

公开(公告)日：2016-03-29

申请号：US13943006

申请日：2013-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： David Seo ,  Ho-jung Kim ,  Hyun-jong Chung ,  Seong-jun Park ,  Kyung-eun Byun ,  Hyun-jae Song ,  Jin-seong Heo

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/772 ,  H01L29/872 ,  H01L29/88 ,  H01L29/40

CPC classification number: H01L29/1606 ,  H01L29/407 ,  H01L29/66977 ,  H01L29/772 ,  H01L29/872 ,  H01L29/88

Abstract: A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Abstract translation: 存储器件包括具有源电极，漏电极和栅电极的石墨烯开关器件。 石墨烯开关器件包括形成在漏电极和沟道之间的从源电极朝向漏电极的方向上的肖特基势垒。 存储器件不需要包括额外的存储元件。