公开(公告)号：US20240178068A1

公开(公告)日：2024-05-30

申请号：US18383940

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungju HWANG ,  Shigenobu Maeda ,  Myoungkyu PARK

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/0886

Abstract: A method of manufacturing a semiconductor device includes: forming a plurality of first mandrel patterns at a first mandrel pitch on a substrate; forming a first fin group and a first dummy fin group by patterning the substrate, wherein the first fin group is adjacent to the first dummy fin group in a first direction; and removing the first dummy fin group, wherein the first fin group includes a first fin and a second fin adjacent to each other and arranged at a first fin pitch in the first direction. The first dummy fin group includes a first dummy fin and a second dummy fin adjacent to each other and arranged at the first fin pitch in the first direction. The second fin and the first dummy fin, which is adjacent to the second fin, are arranged at a second fin pitch that is greater than the first fin pitch.

公开(公告)号：US10749000B2

公开(公告)日：2020-08-18

申请号：US15911182

申请日：2018-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shigenobu Maeda ,  Seunghan Seo ,  Yeohyun Sung

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/165 ,  H01L29/267 ,  H01L29/778 ,  H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/22 ,  H01L29/78 ,  H01L29/51

Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

公开(公告)号：US09627314B2

公开(公告)日：2017-04-18

申请号：US14986872

申请日：2016-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min Choi ,  Shigenobu Maeda

IPC: H01L23/525 ,  H01L23/62 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/62 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

公开(公告)号：US09466724B2

公开(公告)日：2016-10-11

申请号：US14704485

申请日：2015-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changjae Yang ,  Shigenobu Maeda ,  Changhwa Kim ,  Youngmoon Choi

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/7853 ,  H01L29/045 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: According to an exemplary embodiment of the present embodiment, a semiconductor device is provided as follows. An active fin protrudes from a substrate, extending in a direction. A gate structure crosses a first region of the active fin. A source/drain is disposed on a second region of the active fin. The source/drain includes upper surfaces and vertical side surfaces. The vertical side surfaces are in substantially parallel with side surfaces of the active fin.

Abstract translation: 根据本实施例的示例性实施例，提供如下的半导体器件。 主动翅片从沿着方向延伸的基底突出。 栅极结构与有源鳍片的第一区域交叉。 源极/漏极设置在有源鳍片的第二区域上。 源极/漏极包括上表面和垂直侧面。 垂直侧表面基本上平行于活动翅片的侧表面。

公开(公告)号：US09093306B2

公开(公告)日：2015-07-28

申请号：US14337532

申请日：2014-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Jeong Hwan Yang

IPC: H01L29/94 ,  H01L29/76 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

Abstract translation: 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

公开(公告)号：US20250151304A1

公开(公告)日：2025-05-08

申请号：US19009795

申请日：2025-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

IPC: H10D30/01 ,  H10D30/62 ,  H10D84/01 ,  H10D84/03

Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.

公开(公告)号：US12218223B2

公开(公告)日：2025-02-04

申请号：US17877251

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.

公开(公告)号：US20210066454A1

公开(公告)日：2021-03-04

申请号：US17098412

申请日：2020-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  B82Y10/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

公开(公告)号：US09893186B2

公开(公告)日：2018-02-13

申请号：US15224313

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

公开(公告)号：US20170352728A1

公开(公告)日：2017-12-07

申请号：US15686838

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Sun Lee ,  Chang-Woo Sohn ,  Chul-Sung Kim ,  Shigenobu Maeda ,  Young-Moon Choi ,  Hyo-Seok Choi ,  Sang-Jin Hyun

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/165 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.