公开(公告)号：US10403717B2

公开(公告)日：2019-09-03

申请号：US15686838

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Sun Lee ,  Chang-Woo Sohn ,  Chul-Sung Kim ,  Shigenobu Maeda ,  Young-Moon Choi ,  Hyo-Seok Choi ,  Sang-Jin Hyun

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/417

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

公开(公告)号：US20190043959A1

公开(公告)日：2019-02-07

申请号：US15871628

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Gon Lee ,  Ryuji Tomita ,  Chul-Sung Kim ,  Sang-Jin Hyun

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.

公开(公告)号：US10134856B2

公开(公告)日：2018-11-20

申请号：US15254297

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da-Il Eom ,  Jeong-Ik Kim ,  Ja-Hum Ku ,  Chul-Sung Kim ,  Jun-Ki Park ,  Sang-Jin Hyun

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12

Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.

公开(公告)号：US20170352728A1

公开(公告)日：2017-12-07

申请号：US15686838

申请日：2017-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Sun Lee ,  Chang-Woo Sohn ,  Chul-Sung Kim ,  Shigenobu Maeda ,  Young-Moon Choi ,  Hyo-Seok Choi ,  Sang-Jin Hyun

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/165 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

公开(公告)号：US10283600B2

公开(公告)日：2019-05-07

申请号：US15871628

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Gon Lee ,  Ryuji Tomita ,  Chul-Sung Kim ,  Sang-Jin Hyun

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.

公开(公告)号：US20170365555A1

公开(公告)日：2017-12-21

申请号：US15389856

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hun Choi ,  Jeong-Ik Kim ,  Chul-Sung Kim ,  Jae-Eun Lee ,  Sang-Jin Hyun

IPC: H01L23/535 ,  H01L23/532 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

Abstract: Semiconductor devices may include a structure on a substrate, an insulating interlayer, a metal silicide pattern, a first barrier pattern, a second barrier pattern and a metal pattern. The structure may include silicon. The insulating interlayer may include a contact hole exposing a surface of the structure. The metal silicide pattern may be in a lower portion of the contact hole, and the metal silicide pattern may directly contact the exposed surface of the structure. The first barrier pattern may directly contact an upper surface of the metal silicide pattern and a sidewall of the contact hole. The first barrier pattern may include a metal nitride. The second barrier pattern may be formed on the first barrier pattern. The second barrier pattern may include a metal nitride. The metal pattern may be formed on the second barrier pattern. The metal pattern may be in the contact hole.

公开(公告)号：US09876094B2

公开(公告)日：2018-01-23

申请号：US14984037

申请日：2015-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok-Han Bae ,  Kyung-Soo Kim ,  Chul-Sung Kim ,  Woo-Cheol Shin ,  Hwi-Chan Jun

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.