公开(公告)号：US09666289B2

公开(公告)日：2017-05-30

申请号：US15049526

申请日：2016-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Eun Lee ,  Sunghoon Kim

IPC: G11C16/06 ,  H01L27/115 ,  G11C16/14 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  G11C5/02 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C5/025 ,  G11C16/0483 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53271 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor device may include a peripheral region including a lower substrate and a peripheral circuit provided thereon and a cell region including an upper substrate and a cell array provided thereon. The cell region may be stacked on the peripheral region. When an operation signal is applied to the cell region from the peripheral region, at least a portion of the peripheral and cell regions may be used as a ground pattern applied with a ground signal, thereby being in an electrical ground state.

公开(公告)号：US11721669B2

公开(公告)日：2023-08-08

申请号：US16877169

申请日：2020-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Heo ,  Jae-Eun Lee ,  Yeongkwon Ko ,  Donghoon Won

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L24/29 ,  H01L2224/94

Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.

公开(公告)号：US20170365555A1

公开(公告)日：2017-12-21

申请号：US15389856

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hun Choi ,  Jeong-Ik Kim ,  Chul-Sung Kim ,  Jae-Eun Lee ,  Sang-Jin Hyun

IPC: H01L23/535 ,  H01L23/532 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

Abstract: Semiconductor devices may include a structure on a substrate, an insulating interlayer, a metal silicide pattern, a first barrier pattern, a second barrier pattern and a metal pattern. The structure may include silicon. The insulating interlayer may include a contact hole exposing a surface of the structure. The metal silicide pattern may be in a lower portion of the contact hole, and the metal silicide pattern may directly contact the exposed surface of the structure. The first barrier pattern may directly contact an upper surface of the metal silicide pattern and a sidewall of the contact hole. The first barrier pattern may include a metal nitride. The second barrier pattern may be formed on the first barrier pattern. The second barrier pattern may include a metal nitride. The metal pattern may be formed on the second barrier pattern. The metal pattern may be in the contact hole.

公开(公告)号：US10394115B2

公开(公告)日：2019-08-27

申请号：US15442780

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kil Yun ,  Sunghoon Kim ,  Jae-Eun Lee ,  Hyangja Yang

IPC: G03F1/36 ,  G06F17/50

Abstract: A method for verifying mask data in a computing device includes receiving layout data, receiving mask data, determining an interaction number between a pattern corresponding to the layout data and a pattern corresponding to the mask data, and detecting an error of the mask data based on the interaction number.

公开(公告)号：US09899409B2

公开(公告)日：2018-02-20

申请号：US15335482

申请日：2016-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Eun Lee ,  Sunghoon Kim

IPC: G11C16/08 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L24/05 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/145 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2924/00012

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.