公开(公告)号：US10134856B2

公开(公告)日：2018-11-20

申请号：US15254297

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da-Il Eom ,  Jeong-Ik Kim ,  Ja-Hum Ku ,  Chul-Sung Kim ,  Jun-Ki Park ,  Sang-Jin Hyun

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12

Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.

公开(公告)号：US20180233567A1

公开(公告)日：2018-08-16

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/485 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

公开(公告)号：US10276675B2

公开(公告)日：2019-04-30

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/78 ,  H01L29/66

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.