公开(公告)号：US09917174B2

公开(公告)日：2018-03-13

申请号：US15442871

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Uk Jang ,  Gi-Gwan Park ,  Ho-Sung Son ,  Dong-Suk Shin

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L21/26506 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, an isolation pattern may be formed on a substrate to define a plurality of active patterns. The active patterns may protrude from the isolation pattern. A preliminary polysilicon layer may be formed on the active patterns to fill a gap between adjacent ones of the active patterns. Ions having no conductivity may be implanted into the preliminary polysilicon layer to form a polysilicon layer having no void. The active patterns maintain their crystalline state during the implanting of the ions. The polysilicon layer may be patterned to form a dummy gate structure on the active pattern. A source/drain region may be formed at an upper portion of the active patterns adjacent to sides of the dummy gate structure.

公开(公告)号：US20180233567A1

公开(公告)日：2018-08-16

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/485 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

公开(公告)号：US10411011B2

公开(公告)日：2019-09-10

申请号：US16028080

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kook-Tae Kim ,  Ho-Sung Son ,  Dong-Suk Shin ,  Hyun-Jun Sim ,  Ju-Ri Lee ,  Sung-Uk Jang

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/167 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8238

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.

公开(公告)号：US10276675B2

公开(公告)日：2019-04-30

申请号：US15949137

申请日：2018-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/16 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/78 ,  H01L29/66

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

公开(公告)号：US10043806B2

公开(公告)日：2018-08-07

申请号：US15276274

申请日：2016-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kook-Tae Kim ,  Ho-Sung Son ,  Dong-Suk Shin ,  Hyun-Jun Sim ,  Ju-Ri Lee ,  Sung-Uk Jang

IPC: H01L29/15 ,  H01L31/0312 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L21/8238

Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.