公开(公告)号：US10115806B2

公开(公告)日：2018-10-30

申请号：US15165016

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Hwa Kim ,  Joon-Gon Lee ,  Inchan Hwang

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a substrate with lower structures, an insulation layer covering the lower structures on the substrate, a contact hole through the insulation layer partially exposing the substrate, and a contact structure contacting the substrate through the contact hole, the contact structure including a barrier pattern having an upper barrier on an upper portion of a sidewall of the contact hole, and a lower barrier filling a lower portion of the contact hole, and a conductive contact pattern filling an upper portion of the contact hole defined by the upper barrier and the lower barrier.

公开(公告)号：US09728465B2

公开(公告)日：2017-08-08

申请号：US14873456

申请日：2015-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Gon Lee ,  Ryuji Tomita ,  Sang-Jin Hyun ,  Kuo Tai Huang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833

Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer. A second heat treatment process is performed such that the substrate and the second metal layer react with each other to form a third metal-semiconductor composite pattern.

公开(公告)号：US20190043959A1

公开(公告)日：2019-02-07

申请号：US15871628

申请日：2018-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Gon Lee ,  Ryuji Tomita ,  Chul-Sung Kim ,  Sang-Jin Hyun

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.

公开(公告)号：US10283600B2

公开(公告)日：2019-05-07

申请号：US15871628

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Gon Lee ,  Ryuji Tomita ,  Chul-Sung Kim ,  Sang-Jin Hyun

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.