公开(公告)号：US09893186B2

公开(公告)日：2018-02-13

申请号：US15224313

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

公开(公告)号：US10411129B2

公开(公告)日：2019-09-10

申请号：US15877563

申请日：2018-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

公开(公告)号：US20170018645A1

公开(公告)日：2017-01-19

申请号：US15224313

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tae-Yong Kwon ,  Sang-Su Kim ,  Jae-Hoo Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.

Abstract translation: 形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。 场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。 形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。 所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。