公开(公告)号：US10084051B2

公开(公告)日：2018-09-25

申请号：US15133424

申请日：2016-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjine Park ,  Jae-Hwan Lee ,  Yongsun Ko

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/42356 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure on a substrate, device isolation patterns on the substrate at opposite sides of the fin structure, a gate electrode intersecting the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and gate spacers on opposite sidewalls of the gate electrode, wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than bottom surfaces of the gate spacers.

公开(公告)号：US20160005864A1

公开(公告)日：2016-01-07

申请号：US14723673

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong Kwon ,  Shigenobu Maeda ,  David Seo ,  Jae-Hwan Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7849 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785

Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.

Abstract translation: 可以形成MOSFET，其具有改善载流子迁移率的晶格常数的应变诱导失配。 在示例性实施例中，MOSFET包括不会被凹陷步骤破坏的应变诱导晶格常数失配。 在一些实施例中，源/漏图案在没有凹陷步骤的情况下生长，从而避免与凹陷步骤相关的问题。 或者，可以以不暴露应变松弛缓冲层的顶表面的方式执行凹陷处理。 诸如应变松弛缓冲层或器件隔离层的MOSFET器件层不受凹陷步骤的影响，结果可能将应变施加到沟道区而不会影响随后的形成步骤。

公开(公告)号：US11610966B2

公开(公告)日：2023-03-21

申请号：US16694031

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US09825034B2

公开(公告)日：2017-11-21

申请号：US15298288

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan Lee ,  Sangsu Kim

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L21/324 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7842 ,  H01L29/785

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

公开(公告)号：US09536950B2

公开(公告)日：2017-01-03

申请号：US14606017

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan Lee ,  Sangsu Kim

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7842 ,  H01L29/785

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract translation: 半导体器件可以包括设置在基板上以容纳硅锗的应变松弛缓冲层，设置在应变松弛缓冲层上的半导体图案，以包括源区域，漏极区域和将源极区域与漏极连接的沟道区域 区域，以及包围沟道区并在衬底和沟道区之间延伸的栅电极。 源极和漏极区域可以含有浓度为30at％或更高的锗。

公开(公告)号：US20140287755A1

公开(公告)日：2014-09-25

申请号：US14223176

申请日：2014-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hyun LIM ,  Young-Hun Kim ,  Jae-Hwan Lee

IPC: H04W36/00

CPC classification number: H04W36/0083 ,  H04W84/045

Abstract: A method and apparatus are provided for setting a neighbor in a Radio Network Controller (RNC) of a mobile communication system. The method includes receiving, from a Node B, a message indicating that a radio link is released; storing source cell information, when restoration of the radio link fails; receiving, from a User Equipment (UE), an RRC cell update message; storing target cell information included in the RRC cell update message; determining whether a neighbor of a source cell and a target cell is set, based on the source cell information and the target cell information; and setting the neighbor by using the source cell information and the target cell information if the neighbor is not set.

Abstract translation: 提供了一种用于在移动通信系统的无线电网络控制器（RNC）中设置邻居的方法和装置。 该方法包括从节点B接收指示无线电链路被释放的消息; 存储源小区信息，当无线链路恢复失败时; 从用户设备（UE）接收RRC小区更新消息; 存储所述RRC小区更新消息中包含的目标小区信息; 基于所述源小区信息和所述目标小区信息来确定源小区和目标小区的邻居是否被设置; 并且如果没有设置邻居，则使用源小区信息和目标小区信息来设置邻居。

公开(公告)号：US10796803B2

公开(公告)日：2020-10-06

申请号：US15436613

申请日：2017-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangjo Lee ,  Hyunsu Kim ,  Jihye Son ,  Moonbae Song ,  Sanghwa Lee ,  Woosang Lee ,  Jae-Hwan Lee ,  Jaeyoun Jeong ,  Bum-Sung Cho

IPC: A63B24/00 ,  A61B5/024 ,  A61B5/11 ,  G16H50/30 ,  H04W4/029 ,  H04M1/725 ,  G16H40/63 ,  G16H20/30 ,  G01C22/02

Abstract: An electronic device includes a housing, with a display exposed through a part of the housing. The housing includes a first motion sensor to detect movement of the housing, a wireless communication circuit, a processor, and a memory that stores instructions to be executed by a processor. The instructions include generating a wireless communication channel with an external electronic device including a second motion sensor; monitoring the movement of the housing to generate first data for a first time period; receiving second data for the first time period through the wireless communication channel; calculating, as a value for the first time period, a value, smaller than the sum of a first value based on the first data and a second value based on the second data; and displaying the calculated value through a user interface displayed on the display.

公开(公告)号：US10074717B2

公开(公告)日：2018-09-11

申请号：US14993212

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0657 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US09391134B2

公开(公告)日：2016-07-12

申请号：US14336084

申请日：2014-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Jae Yang ,  Sang-Su Kim ,  Jae-Hwan Lee ,  Jung-Dal Choi

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/06 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract translation: 翅片场效应晶体管包括分别从第一和第二鳍结构上的衬底，第一和第二栅电极突出的第一鳍结构和第二鳍结构，以及在第一鳍和第二鳍结构中的每一个之间的栅极介电层 以及第一和第二栅电极。 第一和第二鳍结构中的每一个包括衬底上的缓冲图案，缓冲图案上的沟道图案，以及设置在沟道图案和衬底之间的蚀刻停止图案。 蚀刻停止图案包括具有大于缓冲图案的蚀刻电阻率的蚀刻电阻率的材料。

公开(公告)号：US11515390B2

公开(公告)日：2022-11-29

申请号：US16993514

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.