公开(公告)号：US20160268418A1

公开(公告)日：2016-09-15

申请号：US15165372

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  G11C14/00 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

公开(公告)号：US09099304B2

公开(公告)日：2015-08-04

申请号：US14211789

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Eui-chul Hwang ,  Seong-ho Cho ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Ji-hyun Hur

IPC: H01L21/318 ,  H01L21/02 ,  H01L29/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/02362 ,  H01L21/0226 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract translation: 提供一种半导体器件，其包括在化合物半导体层和电介质层之间的扩散阻挡层，以及制造半导体器件的方法，使得半导体器件包括化合物半导体层; 电介质层; 以及包含在化合物半导体层和电介质层之间形成的氧氮化物的扩散阻挡层。

公开(公告)号：US20150028458A1

公开(公告)日：2015-01-29

申请号：US14211789

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Eui-chul Hwang ,  Seong-ho Cho ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Rakib Uddin Mohammad ,  David Seo ,  Moon-seung Yang ,  Ji-hyun Hur

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/02362 ,  H01L21/0226 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract translation: 提供一种半导体器件，其包括在化合物半导体层和电介质层之间的扩散阻挡层，以及制造半导体器件的方法，使得半导体器件包括化合物半导体层; 电介质层; 以及包含在化合物半导体层和电介质层之间形成的氧氮化物的扩散阻挡层。

公开(公告)号：US10141407B2

公开(公告)日：2018-11-27

申请号：US14506041

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： David Seo ,  Ho-jung Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Seong-ho Cho

IPC: H01L27/108 ,  H01L29/66 ,  H01L45/00 ,  H01L29/16 ,  H01L29/68 ,  H01L27/105 ,  H01L29/76

Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

公开(公告)号：US09929239B2

公开(公告)日：2018-03-27

申请号：US15050867

申请日：2016-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Myoung-jae Lee ,  Seong-ho Cho ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Sang-moon Lee ,  Sung-hun Lee ,  Ji-hyun Hur ,  Eui-chul Hwang

IPC: H01L29/51 ,  H01L29/34 ,  H01L29/66 ,  H01L29/20 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/24

CPC classification number: H01L29/34 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28264 ,  H01L21/322 ,  H01L21/3228 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

公开(公告)号：US09379319B2

公开(公告)日：2016-06-28

申请号：US14444083

申请日：2014-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-jae Lee ,  Seong-ho Cho ,  Ho-jung Kim ,  Young-soo Park ,  David Seo ,  In-kyeong Yoo

IPC: H01L29/02 ,  H01L45/00 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00

CPC classification number: H01L29/788 ,  G06N3/049 ,  G06N3/063 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0007 ,  G11C14/0063 ,  G11C16/0433 ,  G11C2213/15 ,  G11C2213/53 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/408 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/512 ,  H01L29/517 ,  H01L29/685 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/147

Abstract: Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Abstract translation: 提供了非易失性存储晶体管和包括非易失性存储晶体管的器件。 非易失性存储晶体管可以包括沟道元件，对应于沟道元件的栅极电极，沟道元件和栅电极之间的栅极绝缘层，栅极绝缘层和栅电极之间的离子物质移动层，以及源极 以及相对于沟道元件彼此分离的漏极。 根据施加到栅电极的电压，发生离子物质移动层处的离子物质的运动。 阈值电压根据离子物质的运动而变化。 非易失性存储晶体管具有多电平特性。

公开(公告)号：US20150061030A1

公开(公告)日：2015-03-05

申请号：US14471900

申请日：2014-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mohammad Rakib Uddin ,  Moon-seung Yang ,  Dong-soo Lee ,  Myoung-jae Lee ,  Seong-ho Cho ,  Eui-chul Hwang

IPC: H01L29/04 ,  H01L27/092 ,  H01L29/16 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/04 ,  H01L21/02381 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76224 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20

Abstract: Provided are semiconductor structures and methods of fabricating the same. The semiconductor structure includes a silicon substrate, at least one semiconductor layer that is grown on the silicon substrate and has a lattice constant in a range from about 1.03 to about 1.09 times greater than that of the silicon substrate, and a buffer layer that is disposed between the silicon substrate and the semiconductor layer and includes a metal silicide compound for lattice matching with the semiconductor layer. Related fabrication methods are also discussed.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括硅衬底，至少一个在硅衬底上生长并具有比硅衬底大约1.03至大约1.09倍的晶格常数的半导体层，以及设置的缓冲层 在硅衬底和半导体层之间，并且包括用于与半导体层进行晶格匹配的金属硅化物化合物。 还讨论了相关的制造方法。

公开(公告)号：US09570359B2

公开(公告)日：2017-02-14

申请号：US14510354

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-seung Yang ,  Mohammad Rakib Uddin ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Seong-ho Cho

IPC: H01L21/20 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L27/092

Abstract: A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.

Abstract translation: 公开了一种衬底结构，包括衬底结构的互补金属氧化物半导体（CMOS）器件以及制造CMOS器件的方法，其中衬底结构包括：衬底，由材料形成的至少一个种子层 包括硼（B）和/或磷（P），以及种子层上的缓冲层。 该衬底结构使得可以减小缓冲层的厚度并且还改善由衬底结构形成的半导体器件的性能特性。