公开(公告)号：US09570359B2

公开(公告)日：2017-02-14

申请号：US14510354

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-seung Yang ,  Mohammad Rakib Uddin ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Seong-ho Cho

IPC: H01L21/20 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L27/092

Abstract: A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.

Abstract translation: 公开了一种衬底结构，包括衬底结构的互补金属氧化物半导体（CMOS）器件以及制造CMOS器件的方法，其中衬底结构包括：衬底，由材料形成的至少一个种子层 包括硼（B）和/或磷（P），以及种子层上的缓冲层。 该衬底结构使得可以减小缓冲层的厚度并且还改善由衬底结构形成的半导体器件的性能特性。

公开(公告)号：US09472624B2

公开(公告)日：2016-10-18

申请号：US13837460

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-youn Kim ,  Joo-sung Kim ,  Moon-seung Yang

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/267

CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/267

Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.

Abstract translation: 一种在第一氮化物半导体层和第二氮化物半导体层之间包括第一氮化物半导体层，第二氮化物半导体层和第三层的半导体结构。 第一氮化物半导体层具有第一镓组成比，第二氮化物半导体层具有与第一金属组成比不同的第二镓组成比，并且第三层具有大于第一镓的至少一种的第三镓组成比 组成比或第二镓组成比。 该结构还可以包括用于降低至少第二氮化物半导体层所经历的拉伸应力或增加压缩应力的第四层。

公开(公告)号：US09099304B2

公开(公告)日：2015-08-04

申请号：US14211789

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Eui-chul Hwang ,  Seong-ho Cho ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Ji-hyun Hur

IPC: H01L21/318 ,  H01L21/02 ,  H01L29/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/02362 ,  H01L21/0226 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract translation: 提供一种半导体器件，其包括在化合物半导体层和电介质层之间的扩散阻挡层，以及制造半导体器件的方法，使得半导体器件包括化合物半导体层; 电介质层; 以及包含在化合物半导体层和电介质层之间形成的氧氮化物的扩散阻挡层。

公开(公告)号：US20150028458A1

公开(公告)日：2015-01-29

申请号：US14211789

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Eui-chul Hwang ,  Seong-ho Cho ,  Myoung-jae Lee ,  Sang-moon Lee ,  Sung-hun Lee ,  Rakib Uddin Mohammad ,  David Seo ,  Moon-seung Yang ,  Ji-hyun Hur

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/02362 ,  H01L21/0226 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/785

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract translation: 提供一种半导体器件，其包括在化合物半导体层和电介质层之间的扩散阻挡层，以及制造半导体器件的方法，使得半导体器件包括化合物半导体层; 电介质层; 以及包含在化合物半导体层和电介质层之间形成的氧氮化物的扩散阻挡层。

公开(公告)号：US09929239B2

公开(公告)日：2018-03-27

申请号：US15050867

申请日：2016-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-soo Lee ,  Myoung-jae Lee ,  Seong-ho Cho ,  Mohammad Rakib Uddin ,  David Seo ,  Moon-seung Yang ,  Sang-moon Lee ,  Sung-hun Lee ,  Ji-hyun Hur ,  Eui-chul Hwang

IPC: H01L29/51 ,  H01L29/34 ,  H01L29/66 ,  H01L29/20 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/24

CPC classification number: H01L29/34 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/28264 ,  H01L21/322 ,  H01L21/3228 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

公开(公告)号：US09207469B2

公开(公告)日：2015-12-08

申请号：US13973521

申请日：2013-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-seung Yang ,  Seong-ho Cho ,  Mohammad Rakib Uddin

IPC: G02F1/035 ,  G02F1/025

CPC classification number: G02F1/025 ,  G02F2203/60 ,  Y02E10/50

Abstract: An athermal optical modulator includes a waveguide, a ring resonator configured to receive light input from the waveguide and output modulated light to the waveguide, the ring resonator including a ridge unit located at a center of the ring resonator in a vertical section, a first contact connected to one side of the ridge unit and a second contact connected to the other side of the ridge unit, the first contact and the second contact forming paths for applying electricity to the ring resonator to form an electric field in the ring resonator, and a polymer layer covering the ridge unit.

Abstract translation: 一种无热光调制器，包括波导，环形谐振器，其被配置为接收从波导输入的光并将调制光输出到波导，所述环形谐振器包括位于所述环形谐振器的垂直部分的中心的脊单元，所述第一接触 连接到所述脊单元的一侧，并且连接到所述脊单元的另一侧的第二触点，所述第一触点和所述第二触点形成路径用于向所述环形谐振器施加电力以在所述环形谐振器中形成电场，以及 覆盖脊单元的聚合物层。

公开(公告)号：US20150061030A1

公开(公告)日：2015-03-05

申请号：US14471900

申请日：2014-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mohammad Rakib Uddin ,  Moon-seung Yang ,  Dong-soo Lee ,  Myoung-jae Lee ,  Seong-ho Cho ,  Eui-chul Hwang

IPC: H01L29/04 ,  H01L27/092 ,  H01L29/16 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/04 ,  H01L21/02381 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76224 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20

Abstract: Provided are semiconductor structures and methods of fabricating the same. The semiconductor structure includes a silicon substrate, at least one semiconductor layer that is grown on the silicon substrate and has a lattice constant in a range from about 1.03 to about 1.09 times greater than that of the silicon substrate, and a buffer layer that is disposed between the silicon substrate and the semiconductor layer and includes a metal silicide compound for lattice matching with the semiconductor layer. Related fabrication methods are also discussed.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括硅衬底，至少一个在硅衬底上生长并具有比硅衬底大约1.03至大约1.09倍的晶格常数的半导体层，以及设置的缓冲层 在硅衬底和半导体层之间，并且包括用于与半导体层进行晶格匹配的金属硅化物化合物。 还讨论了相关的制造方法。