公开(公告)号：US09754849B2

公开(公告)日：2017-09-05

申请号：US14581575

申请日：2014-12-23

申请人： INTEL CORPORATION

发明人： Plory Huang ,  Henry Su ,  Chee Key Chung ,  Ryan Ong ,  Jones Wang ,  Daniel Hsieh

IPC分类号： H01L23/02 ,  H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/15

CPC分类号： H01L23/13 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15311

摘要： An organic-inorganic hybrid structure is described for integrated circuit packages. In one example, an integrated circuit package includes a ceramic frame having a top side and a bottom side, the top side having a pocket with a bottom floor and a plurality of conductive through holes in the bottom floor, an integrated circuit die attached to the bottom floor over the conductive through holes, and a redistribution layer on the bottom side connected to the conductive through holes.

公开(公告)号：US09741694B2

公开(公告)日：2017-08-22

申请号：US14985461

申请日：2015-12-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chen-Hua Yu ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC分类号： H01L21/68 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/165 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572

摘要： A semiconductor structure and a method for forming the same are provided. The method comprises: providing a first semiconductor workpiece; bonding a second semiconductor workpiece to a first surface of the first semiconductor workpiece; forming a first electrically conductive via through the second semiconductor workpiece to the first semiconductor workpiece; bonding a third semiconductor workpiece to a second surface of the first semiconductor workpiece, the second surface being opposite to the first surface; and forming a second electrically conductive via through the first semiconductor workpiece and the third semiconductor workpiece to the second semiconductor workpiece such that the first electrically conductive via and the second electrically conductive via are electrically connected.

公开(公告)号：US20170236783A1

公开(公告)日：2017-08-17

申请号：US15581799

申请日：2017-04-28

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Yi-Wei Liu ,  Yan-Heng Chen ,  Mao-Hua Yeh ,  Hung-Wen Liu ,  Yi-Che Lai

IPC分类号： H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

CPC分类号： H01L23/5389 ,  H01L21/31053 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

摘要： The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

公开(公告)号：US09728527B2

公开(公告)日：2017-08-08

申请号：US14925807

申请日：2015-10-28

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC分类号： H01L23/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L21/311 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/32 ,  H01L24/33 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02317 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/08146 ,  H01L2224/0823 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/13616 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/24147 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4805 ,  H01L2224/48108 ,  H01L2224/48149 ,  H01L2224/4903 ,  H01L2224/49426 ,  H01L2224/73201 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/386 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/01082 ,  H01L2224/05 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/45616 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/45099

摘要： An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

公开(公告)号：US20170221835A1

公开(公告)日：2017-08-03

申请号：US15267233

申请日：2016-09-16

申请人： Samsung Electro-Mechanics Co., Ltd.

发明人： Do Jae YOO ,  Hee Jung JUNG ,  Jong In RYU ,  Ki Joo SIM

IPC分类号： H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L25/18 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/552 ,  H01L21/4817 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49805 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15159 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025

摘要： A double-sided package module includes a substrate, a first sealing member, a second sealing member, and an extension portion. The substrate includes electronic components positioned on a first surface and a second surface of the substrate. The first sealing member and the second sealing member are positioned on the first surface and the second surface, respectively. The extension portion protrudes from a lateral surface of the substrate into a space between the first sealing member and the second sealing member.

公开(公告)号：US09721933B2

公开(公告)日：2017-08-01

申请号：US15361861

申请日：2016-11-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen

IPC分类号： H01L21/44 ,  H01L25/10 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/544 ,  H01L23/58 ,  H01L21/768 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L23/585 ,  H01L24/06 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad.

公开(公告)号：US20170207159A1

公开(公告)日：2017-07-20

申请号：US15477265

申请日：2017-04-03

申请人： Invensas Corporation

发明人： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/373 ,  H01L23/00 ,  H01L25/065

CPC分类号： H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

摘要： Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US20170194292A1

公开(公告)日：2017-07-06

申请号：US15058818

申请日：2016-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Chi-Hsi Wu

IPC分类号： H01L25/065 ,  H01L21/78 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/3511

摘要： A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

公开(公告)号：US20170194290A1

公开(公告)日：2017-07-06

申请号：US15464011

申请日：2017-03-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Kuo-Chung Yee

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/56

CPC分类号： H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

摘要： An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

公开(公告)号：US09698093B2

公开(公告)日：2017-07-04

申请号：US14833148

申请日：2015-08-24

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Chee Seng Foong ,  Ly Hoon Khoo ,  Wen Shi Koh ,  Wai Yew Lo ,  Zi Song Poh ,  Kai Yun Yow

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/544 ,  G03F9/00 ,  H01L23/538 ,  H01L21/768

CPC分类号： H01L23/49838 ,  G03F9/7073 ,  G03F9/7084 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76816 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/54486 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2224/45099

摘要： A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.