公开(公告)号：US09978669B2

公开(公告)日：2018-05-22

申请号：US15198111

申请日：2016-06-30

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Chee Seng Foong

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49555 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49551 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. Leads in a first subset of the leads alternate with leads in a second subset of the leads. The inner portion of the first subset of the leads is bent. The die pad, the inner portion of the leads, and only a first portion of the openings adjacent the inner portion of the leads are encapsulated. A second portion of the openings and the output portions of the leads form a dam bar for the encapsulating material.

公开(公告)号：US09698093B2

公开(公告)日：2017-07-04

申请号：US14833148

申请日：2015-08-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Chee Seng Foong ,  Ly Hoon Khoo ,  Wen Shi Koh ,  Wai Yew Lo ,  Zi Song Poh ,  Kai Yun Yow

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/544 ,  G03F9/00 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L23/49838 ,  G03F9/7073 ,  G03F9/7084 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76816 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/54486 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2224/45099

Abstract: A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.

公开(公告)号：US20170062311A1

公开(公告)日：2017-03-02

申请号：US14833149

申请日：2015-08-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Chee Seng Foong ,  Yin Kheng Au ,  Ly Hoon Khoo ,  Wen Shi Koh ,  Pei Fan Tong

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/49541 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49095 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/0665

Abstract: A packaged IC device has a power bar assembly with one or more power distribution bars, mounted on top of the IC die, which enables assembly using a lead frame that does not include any power distribution bars. External power supply voltages are brought to the IC die by (i) a corresponding first bond wire that connects a lead frame lead to a corresponding die-mounted power distribution bar and (ii) a corresponding second bond wire that connects the power distribution bar to a corresponding bond pad on the IC die. As such, different types of packaged IC devices having different numbers and/or configurations of power distribution bars can be assembled using a single, generic lead frame design having a die pad, tie bars, and leads, but no power distribution bars.

Abstract translation: 封装的IC器件具有安装在IC管芯顶部的具有一个或多个配电棒的电力棒组件，其能够使用不包括任何配电棒的引线框组装。 外部电源电压通过（i）将引线框引线连接到相应的芯片安装的配电棒的相应的第一接合线引导到IC管芯，以及（ii）将配电棒连接到 IC芯片上的相应的焊盘。 因此，具有不同数量和/或配置配电棒的不同类型的封装IC器件可以使用具有管芯焊盘，连接条和引线但没有配电棒的单一的通用引线框架设计来组装。