公开(公告)号：US09754843B1

公开(公告)日：2017-09-05

申请号：US15205535

申请日：2016-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Ajey P. Jacob

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L27/092 ,  H01L29/49 ,  H01L21/302 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L21/823885 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

公开(公告)号：US09748359B1

公开(公告)日：2017-08-29

申请号：US15336479

申请日：2016-10-27

Applicant: International Business Machines Corporation

Inventor： Oleg Gluschenkov ,  Sanjay C. Mehta ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L21/02255 ,  H01L21/2236 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642

Abstract: A silicon layer is formed on a surface of each bottom source/drain region that is present at the footprint of a semiconductor fin. A first set of atoms (nitrogen atoms or carbon atoms) and a second set of atoms (boron atoms and/or carbon atoms) are then ion implanted into the silicon layer and the bottom source/drain regions. An anneal is then performed to convert the silicon layer into a bottom dielectric spacer that is composed of a reaction product of silicon, the first set of atoms and the second set of atoms, while converting each bottom source/drain region into a bottom source/drain structure that includes a first region and a second region. The second region is composed of a doped semiconductor material and at least one of the boron atoms and the carbon atoms; no measurable nitrogen tail and/or oxygen tail is present in the source/drain structures.

公开(公告)号：US09741621B2

公开(公告)日：2017-08-22

申请号：US15430174

申请日：2017-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Feng Fu ,  De-Fang Chen ,  Yu-Chan Yen ,  Chia-Ying Lee ,  Chun-Hung Lee ,  Huan-Just Lin

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/78642

Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.

公开(公告)号：US20170236911A1

公开(公告)日：2017-08-17

申请号：US15583981

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/266 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/41741 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78642

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

公开(公告)号：US09735246B1

公开(公告)日：2017-08-15

申请号：US15152144

申请日：2016-05-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/15 ,  H01L21/336 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/4991 ,  C23C14/0652 ,  C23C14/081 ,  C23C14/083 ,  C23C14/588 ,  C23C16/345 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31055 ,  H01L21/32115 ,  H01L23/315 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78654 ,  H01L2029/42388

Abstract: Transistors and method of forming he same include forming a fin on a bottom source/drain region having a channel region and a sacrificial region on the channel region. A gate stack is formed on sidewalls of the channel region. A gate conductor is formed in contact with the gate stack that has a top surface that meets a middle point of sidewalls of the sacrificial region. The sacrificial region is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor having airgaps above the gate stack.

公开(公告)号：US20170229558A1

公开(公告)日：2017-08-10

申请号：US15017868

申请日：2016-02-08

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Huiming Bu ,  Fee Li Lie ,  Shogo Mochizuki ,  Junli Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/417 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L29/66795 ,  H01L21/22 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.

公开(公告)号：US20170213836A1

公开(公告)日：2017-07-27

申请号：US15482610

申请日：2017-04-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/108 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US09716181B2

公开(公告)日：2017-07-25

申请号：US15176611

申请日：2016-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Phil Ouk Nam ,  Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-l Lee ,  JongHeun Lim ,  Wonbong Jung

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78672 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1207 ,  H01L29/78642

Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.

公开(公告)号：US09711650B2

公开(公告)日：2017-07-18

申请号：US15190803

申请日：2016-06-23

Applicant: SanDisk Technologies LLC

Inventor： Seiji Shimabukuro

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  H01L23/535 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/78642 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/77 ,  H01L23/535 ,  H01L27/115 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/16

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath each gate, a single gap fill dielectric layer extends vertically from a lower surface of the gate, at least partially separating the gate from the underlying global bit line. Between horizontally adjacent pillars, this same dielectric layer extends from its same lower level beneath the gates vertically to a level of the upper source/drain region.

公开(公告)号：US20170194447A1

公开(公告)日：2017-07-06

申请号：US15464698

申请日：2017-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jean-Pierre Colinge ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/788 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/42392 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28273 ,  H01L27/1214 ,  H01L29/0676 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66742 ,  H01L29/66825 ,  H01L29/78642 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7889

Abstract: A method comprises doping a lower portion of a nanowire to form a first drain/source region, wherein the nanowire is formed over a substrate, doping an upper portion of the nanowire to form a second drain/source region, doping a middle portion of the nanowire to form a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, forming a ring-shaped gate structure surrounding a lower portion of the channel region, wherein the ring-shaped gate structure comprises a vertical portion of a first work-function metal layer and depositing a low-resistivity gate metal layer over a horizontal portion of the first work-function metal layer, wherein the low-resistivity gate metal layer is electrically coupled to the vertical portion of the first work-function metal layer through the horizontal portion of the first work-function metal layer.