公开(公告)号：US20160086902A1

公开(公告)日：2016-03-24

申请号：US14495575

申请日：2014-09-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： GIA-HER LU ,  LIANG-CHEN LIN ,  TUNG-CHIN YEH ,  JYUN-LIN WU ,  TUNG-JIUN WU

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06181 ,  H01L2224/10126 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32106 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/92225 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2224/81805 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/11 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2221/68304 ,  H01L2224/83 ,  H01L21/56 ,  H01L21/304 ,  H01L2221/68368

Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.

Abstract translation: 半导体封装结构包括半导体衬底，其包括从半导体衬底的第一表面延伸到第二表面的多个通过衬底通孔（TSV），其中第二表面与第一表面相对; 在第二表面上的多个导电凸块并连接到相应的TSV上; 在第二表面上的聚合物层并且围绕相应的导电凸块的下部。 聚合物层包括被构造为覆盖半导体衬底的外围区域的橡皮布的第一部分; 以及半导体衬底的芯区域中的第二部分，并且被配置为多个隔离带，其中每个隔离带围绕相应的导电凸块。

公开(公告)号：US09129982B2

公开(公告)日：2015-09-08

申请号：US14659915

申请日：2015-03-17

Applicant: ROHM CO., LTD.

Inventor： Kenichi Yoshimochi

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/423

CPC classification number: H01L21/76237 ,  H01L21/76205 ,  H01L21/763 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/11896 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66106 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/4911 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract translation: 半导体器件包括：第一导电型半导体层，包括其中形成有杂质区的晶体管的有源区和围绕有源区的边缘区;形成在有源区和边界之间的第二导电型沟道层; 形成半导体层的前表面，形成在有源区中的至少一个栅极沟槽，以从半导体层的前表面延伸通过沟道层，形成在栅极沟槽的内表面上的栅极绝缘膜， 形成在栅极沟槽中的栅极绝缘膜内部的栅极电极，以及布置在有源区域和边缘区域之间的至少一个隔离沟槽，以围绕有源区域并从半导体层的前表面延伸穿过沟道层， 隔离沟槽的深度等于栅极沟槽的深度。

公开(公告)号：US20150235969A1

公开(公告)日：2015-08-20

申请号：US14551098

申请日：2014-11-24

Applicant: Hanmin Zhang ,  Qingchun He ,  Dehong Ye ,  Fei Zong

Inventor： Hanmin Zhang ,  Qingchun He ,  Dehong Ye ,  Fei Zong

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/12 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/033 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05564 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor wafer having multiple dies has a partially metallized backside. After wafer dicing, each of the multiple dies has, on its backside, a metallized area surrounded by a peripheral non-metallization ring. The non-metallization ring allows for easier optical inspection of the dies for determining the extent of any backside chipping caused by the wafer dicing. The peripheral non-metallization rings are generated by not metalizing the areas flanking the saw streets of the wafer.

Abstract translation: 具有多个管芯的半导体晶片具有部分金属化的背面。 在晶片切割之后，多个管芯中的每一个在其背面具有被外围非金属化环包围的金属化区域。 非金属化环允许更容易地对模具进行光学检查，以确定由晶片切割引起的任何背面切屑的程度。 周边的非金属化环是通过不使晶片的锯条的两侧的区域金属化而产生的。

公开(公告)号：US20150130052A1

公开(公告)日：2015-05-14

申请号：US14092796

申请日：2013-11-27

Applicant: IMEC

Inventor： Mikael Detalle

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/17517 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/04941

Abstract: The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.

Abstract translation: 所公开的技术涉及形成在诸如集成电路芯片或插入器基板的半导体部件上的柱状微胶囊以及形成柱状微丸的方法。 一方面，在半导体部件上形成柱状微型块的方法包括提供半导体部件，其中半导体部件具有上金属化层，并且金属化层具有接触面积。 该方法还包括在金属化层上形成钝化层。 该方法还包括通过钝化层形成多个开口，使得接触区域在开口的底部露出。 所述方法还包括在所述接触区域上形成所述微型块，其中所述微型小块通过所述开口与所述接触区域形成电连接。

公开(公告)号：US20140295625A1

公开(公告)日：2014-10-02

申请号：US14301521

申请日：2014-06-11

Applicant: ROHM CO., LTD.

Inventor： Kenichi YOSHIMOCHI

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76237 ,  H01L21/76205 ,  H01L21/763 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/11896 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66106 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/4911 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract translation: 半导体器件包括：第一导电型半导体层，包括其中形成有杂质区的晶体管的有源区和围绕有源区的边缘区;形成在有源区和边界之间的第二导电型沟道层; 形成半导体层的前表面，形成在有源区中的至少一个栅极沟槽，以从半导体层的前表面延伸通过沟道层，形成在栅极沟槽的内表面上的栅极绝缘膜， 形成在栅极沟槽中的栅极绝缘膜内部的栅极电极，以及布置在有源区域和边缘区域之间的至少一个隔离沟槽，以围绕有源区域并且从半导体层的前表面延伸穿过沟道层， 隔离沟槽的深度等于栅极沟槽的深度。

公开(公告)号：US20140131886A1

公开(公告)日：2014-05-15

申请号：US13758359

申请日：2013-02-04

Applicant: Jong Sik Paek ,  Doo Hyun Park

Inventor： Jong Sik Paek ,  Doo Hyun Park

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/50 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16104 ,  H01L2224/16146 ,  H01L2224/16221 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2221/683 ,  H01L21/304 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness.

Abstract translation: 提供半导体器件及其制造方法。 在第一半导体管芯和第二半导体管芯彼此堆叠之后，移除载体，然后形成第一密封剂，使得与从载体从具有 薄的厚度。

公开(公告)号：US08592310B2

公开(公告)日：2013-11-26

申请号：US13240040

申请日：2011-09-22

Applicant: Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05609 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.

Abstract translation: 在制造半导体器件的方法中，制备具有与第一表面相对的第一表面和第二表面的衬底。 在基板的形成有通孔的区域中形成牺牲层图案。 牺牲层图案在基板的厚度方向上从基板的第一表面延伸。 在衬底的第一表面上形成上部布线层。 上部布线层包括牺牲层图案上的布线。 部分去除衬底的第二表面以暴露牺牲层图案。 牺牲层图案从基板的第二表面移除以形成露出布线的开口。 通孔形成在开口中以与布线电连接。

公开(公告)号：US20130186754A1

公开(公告)日：2013-07-25

申请号：US13353523

申请日：2012-01-19

Applicant: Kristin M. Ackerson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Yen Li Lim

Inventor： Kristin M. Ackerson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Yen Li Lim

IPC: G01N27/403 ,  G01N27/416 ,  H01L21/283

CPC classification number: G01N27/3276 ,  G01N27/22 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05157 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/13101 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A biosensor capacitor, including a dielectric layer; a first metal layer in the dielectric layer; a passivation layer over the dielectric layer and the first metal layer; an isolation layer over the passivation layer; a probe DNA electrode connected to the first metal layer; a counter electrode connected to the first metal layer wherein the counter electrode forms an enclosure around the probe DNA electrode; and a bond pad connected to the first metal layer.

Abstract translation: 一种生物传感器电容器，包括介电层; 介电层中的第一金属层; 在所述介​​电层和所述第一金属层上的钝化层; 钝化层上的隔离层; 连接到第一金属层的探针DNA电极; 连接到所述第一金属层的对电极，其中所述对电极围绕所述探针DNA电极形成外壳; 以及连接到第一金属层的接合焊盘。

公开(公告)号：US20120326207A1

公开(公告)日：2012-12-27

申请号：US13491581

申请日：2012-06-07

Applicant: Kenichi Yoshimochi

Inventor： Kenichi Yoshimochi

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L21/76237 ,  H01L21/76205 ,  H01L21/763 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/11896 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66106 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/4911 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract translation: 半导体器件包括：第一导电型半导体层，包括其中形成有杂质区的晶体管的有源区和围绕有源区的边缘区;形成在有源区和边界之间的第二导电型沟道层; 形成半导体层的前表面，形成在有源区中的至少一个栅极沟槽，以从半导体层的前表面延伸通过沟道层，形成在栅极沟槽的内表面上的栅极绝缘膜， 形成在栅极沟槽中的栅极绝缘膜内部的栅极电极，以及布置在有源区域和边缘区域之间的至少一个隔离沟槽，以围绕有源区域并且从半导体层的前表面延伸穿过沟道层， 隔离沟槽的深度等于栅极沟槽的深度。

公开(公告)号：US08264078B2

公开(公告)日：2012-09-11

申请号：US13324499

申请日：2011-12-13

Applicant: Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

Inventor： Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/03 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552

Abstract: In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The areal density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad.

Abstract translation: 在一个实施例中，金属结构的子垫组件位于金属垫的正下方。 子焊盘组件包括邻接金属焊盘的上层金属线结构，位于上层金属线结构下方的下层金属线结构，以及一组在下层金属线结构之间提供电连接的金属通孔 在上层金属线结构下方。 在另一个实施例中，C4球的可靠性通过使用具有一组集成金属通孔的金属焊盘结构而被增强，所述集成金属通孔被分段和分配以便于在C4球内均匀的电流密度分布。 在金属焊盘的中心部分，多个金属通孔中的横截面面积的面密度高于在金属焊盘的平面部分的周边部分。