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    BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same
    3.
    发明授权
    BI-CMOS gate array semiconductor integrated circuits and internal cell structure involved in the same 失效
    BI-CMOS门阵列半导体集成电路和内部单元结构相同

    公开(公告)号：US5497014A

    公开(公告)日：1996-03-05

    申请号：US300132

    申请日：1994-09-02

    Applicant: Takayuki Momose

    Inventor： Takayuki Momose

    IPC: H01L21/82 ,  H01L27/118 ,  H01L27/10 ,  H01L29/76

    CPC classification number: H01L27/11896

    Abstract: The invention provides a Bi-CMOS gate array semiconductor integrated circuit chip including a peripheral region including an input/output circuit region and a bonding pad region and an internal cell structure provided within an internal cell region involved in the semiconductor integrated circuit chip. The internal cell structure comprises MOS transistor cell units including a plurality of MOS transistors and bipolar transistor cell units including a plurality of bipolar transistors wherein a distribution ratio in the number of the MOS transistor cell units to the bipolar transistor cell units has such a variation that the distributed ratio is high in a region that requires driving of almost no or a small load while the distributed ratio is low in a region that requires driving of a large load.

    Abstract translation: 本发明提供了一种Bi-CMOS栅极阵列半导体集成电路芯片，其包括包括输入/​​输出电路区域和焊盘区域的外围区域和设置在涉及半导体集成电路芯片的内部单元区域内的内部单元结构。 内部单元结构包括包括多个MOS晶体管的MOS晶体管单元单元和包括多个双极晶体管的双极晶体管单元单元，其中MOS晶体管单元单元与双极晶体管单元单元的分配比例具有这样的变化： 在需要大负载驱动的区域中，分散比低的区域中，分布比例高，需要几乎不需要驱动或小负载的区域。

    Basic cell for BiCMOS gate array
    4.
    发明授权
    Basic cell for BiCMOS gate array 失效
    BiCMOS门阵列的基本单元

    公开(公告)号：US5341041A

    公开(公告)日：1994-08-23

    申请号：US743532

    申请日：1991-08-08

    Applicant: Abbas El Gamal

    Inventor： Abbas El Gamal

    IPC: H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L27/118 ,  H03K3/356 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/173 ,  H03K19/177 ,  H03K19/02

    CPC classification number: H03K19/09448 ,  H01L27/11896 ,  H03K19/1735

    Abstract: An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.

    Abstract translation: 本文公开了一种用于掩模可编程门阵列的改进的单元。 优选的单元包括两个计算部分，每个部分包括两对中等尺寸的P和N沟道晶体管，两个小N沟道晶体管和单个小P沟道晶体管。 每个单元还包括含有单个双极上拉晶体管，大N沟道下拉晶体管和小P沟道晶体管的高效率驱动部分。 通过使用该单元，实现了每个管芯面积极高的计算能力。

    Semiconductor integrated circuit with bipolar transistors and MOSFETs
    5.
    发明授权
    Semiconductor integrated circuit with bipolar transistors and MOSFETs 失效
    具有双极晶体管和MOSFET的半导体集成电路

    公开(公告)号：US5220187A

    公开(公告)日：1993-06-15

    申请号：US917907

    申请日：1992-07-21

    Applicant: Shuuichi Miyaoka ,  Masanori Odaka ,  Katsumi Ogiue

    Inventor： Shuuichi Miyaoka ,  Masanori Odaka ,  Katsumi Ogiue

    IPC: H01L21/82 ,  H01L27/118 ,  H03K19/0944 ,  H03K19/173

    CPC classification number: H03K19/09448 ,  H01L27/11896

    Abstract: A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value, and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. That is, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting such a design technique has its operating speed raised. An improved structure is also provided for reducing wiring lengths by arranging bipolar transistors in adjacent basic cells to have mirror symmetry with one another. Further, particular gate width relationships are provided between MOSFETs within basic cells for reducing propagation delay and the required occupation area.

    Bipolar transistor/insulated gate transistor hybrid semiconductor device
    8.
    发明授权
    Bipolar transistor/insulated gate transistor hybrid semiconductor device 失效
    双极晶体管/绝缘栅晶体管混合半导体器件

    公开(公告)号：US5272366A

    公开(公告)日：1993-12-21

    申请号：US747864

    申请日：1991-08-20

    Applicant: Toshikazu Sei ,  Yasunori Tanaka ,  Hiroyuki Hara

    Inventor： Toshikazu Sei ,  Yasunori Tanaka ,  Hiroyuki Hara

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/732 ,  H01L27/10 ,  H01L29/76

    CPC classification number: H01L27/11896

    Abstract: A bipolar transistor/insulated gate transistor hybrid semiconductor device comprises a well region formed on a semiconductor substrate to serve as a first active region of a bipolar transistor, an insulated gate transistor having source and drain regions formed in the well region, which acts as a back gate of the insulated gate transistor, and second and third active regions of the bipolar transistor formed in the well region. At least one of the second and third active regions is used in common to one of the source and drain regions of the insulated gate transistor. A plurality of well regions is regularly arranged to constitute a gate array.

    Abstract translation: 双极晶体管/绝缘栅晶体管混合半导体器件包括形成在半导体衬底上的阱区，用作双极晶体管的第一有源区，在阱区中形成源区和漏区的绝缘栅晶体管，其作为 绝缘栅晶体管的背栅，以及形成在阱区中的双极晶体管的第二和第三有源区。 第二和第三有源区域中的至少一个共用于绝缘栅极晶体管的源极和漏极区域中的一个。 规则地布置多个阱区以构成栅极阵列。

    Semiconductor integrated circuit device and manufacturing method of the same
    9.
    发明授权
    Semiconductor integrated circuit device and manufacturing method of the same 失效
    半导体集成电路器件及其制造方法相同

    公开(公告)号：US5168342A

    公开(公告)日：1992-12-01

    申请号：US707974

    申请日：1991-05-23

    Applicant: Manabu Shibata

    Inventor： Manabu Shibata

    IPC: H01L23/528 ,  H01L27/118

    CPC classification number: H01L27/11896 ,  H01L23/528 ,  H01L2924/0002

    Abstract: In a semiconductor integrated circuit device adopting a master slice system, a plurality of lattice points of an X-Y lattice-shaped channel region set by an automatic arrangement and routing system correspond to one input/output terminal of a prescribed basic cell (or logic circuit), thereby a plurality of signal wirings can be connected to the one input/output terminal.

    Abstract translation: 在采用主切片系统的半导体集成电路装置中，由自动布置和布线系统设置的XY格状通道区域的多个点阵对应于规定的基本单元（或逻辑电路）的一个输入/输出端子， 从而多个信号布线可以连接到一个输入/输出端子。

    Method for manufacturing a semiconductor device having isolated islands and its resulting structure
    10.
    发明授权
    Method for manufacturing a semiconductor device having isolated islands and its resulting structure 失效
    用于制造具有隔离岛的半导体器件的方法及其结果

    公开(公告)号：US5031019A

    公开(公告)日：1991-07-09

    申请号：US199860

    申请日：1988-05-27

    Applicant: Daisuke Kosaka ,  Yoshinori Ueda ,  Tetsuo Hikawa ,  Masami Nishikawa

    Inventor： Daisuke Kosaka ,  Yoshinori Ueda ,  Tetsuo Hikawa ,  Masami Nishikawa

    IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L27/118 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11896

    Abstract: A method for manufacturing a Bi-CMOS device by preparing both of bipolar and MOS standard cells in a library is provided. A substrate of a first conductivity type is provided and a plurality of buried layers of a second conductivity type are formed on selected locations of the substrate. Then an epitaxial layer of the first conductivity type is formed on the substrate covering the buried layers. Then a plurality of wells of the second conductivity type are formed in the epitaxial layer such that each of the wells extends through the epitaxial layer from the top surface to at least a portion of the corresponding buried layer to thereby define a plurality of electrically isolated islands in the epitaxial layer. Then a bipolar transistor is formed in at least one of the islands with a MOS transistor formed in at least another of the islands.

    Abstract translation: 提供了一种通过在库中制备双极和MOS标准单元来制造Bi-CMOS器件的方法。 提供第一导电类型的衬底，并且在衬底的选定位置上形成第二导电类型的多个掩埋层。 然后在覆盖埋层的基板上形成第一导电类型的外延层。 然后在外延层中形成第二导电类型的多个阱，使得每个阱从顶表面延伸穿过外延层至相应掩埋层的至少一部分，从而限定多个电隔离岛 在外延层中。 然后在至少一个岛上形成双极晶体管，其中MOS晶体管形成在至少另一个岛中。

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