公开(公告)号：US20200126935A1

公开(公告)日：2020-04-23

申请号：US16162892

申请日：2018-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU

IPC: H01L23/00

Abstract: The present disclosure provides a semiconductor package, including a first conductive feature configured as an I/O terminal of the semiconductor package, a first passivation layer, a capacitor, and a second passivation layer. The first conductive feature includes a redistribution portion and a via portion. The maximum width of the redistribution portion along a first direction is more than 10 times the maximum width of the via portion along the first direction. The first passivation layer is surrounding the via portion of the first conductive feature. The capacitor is substantially within the first passivation layer and electrically coupled to the first conductive feature. The second passivation layer is formed on the first passivation layer and surrounding the redistribution portion of the first conductive feature. A method of manufacturing the semiconductor package is also provided.

公开(公告)号：US20240363677A1

公开(公告)日：2024-10-31

申请号：US18768000

申请日：2024-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU

IPC: H01G4/10 ,  H01G4/228 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01G4/228 ,  H01L21/76832 ,  H01L23/3171 ,  H01L23/5223 ,  H01L23/5226

Abstract: The present disclosure provides a method for forming a semiconductor structure, including forming a bottom terminal, forming a high-k dielectric layer over the bottom terminal, forming a top terminal over the high-k dielectric layer, forming a first passivation layer over the top terminal, forming a first recess penetrating the first passivation layer, the top terminal and the bottom terminal, forming a first etch stop layer over the first passivation layer, forming an opening in the first etch stop layer and over the first recess to expose a portion of the first passivation layer, and forming a conductive material in the first recess and the opening.

公开(公告)号：US20210210447A1

公开(公告)日：2021-07-08

申请号：US17207028

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU ,  MINGNI CHANG ,  MING-YIH WANG ,  YINLUNG LU

IPC: H01L23/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.

公开(公告)号：US20200381378A1

公开(公告)日：2020-12-03

申请号：US16425538

申请日：2019-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU ,  MINGNI CHANG ,  MING-YIH WANG ,  YINLUNG LU

IPC: H01L23/00

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.

公开(公告)号：US20200227368A1

公开(公告)日：2020-07-16

申请号：US16249500

申请日：2019-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor structure includes a substrate; a conductive pad disposed over the substrate; a passivation disposed over the substrate and covering a portion of the conductive pad; a bump pad disposed over the conductive pad and the passivation; a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; and a dielectric member disposed over the passivation and surrounding the conductive pillar.

公开(公告)号：US20220216141A1

公开(公告)日：2022-07-07

申请号：US17142183

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor structure includes: forming an interconnect structure including a metallization layer over a substrate; depositing a first dielectric layer over the metallization layer; depositing a second dielectric layer over and separate from the first dielectric layer; depositing a third dielectric layer over the second dielectric layer, the third dielectric layer having a Young's modulus greater than that of the first and second dielectric layers; forming a capacitor structure over the third dielectric layer; and forming a conductive via extending through the capacitor structure and the first, second and third dielectric layers and electrically coupled to the metallization layer.

公开(公告)号：US20210083041A1

公开(公告)日：2021-03-18

申请号：US17088284

申请日：2020-11-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU

IPC: H01L49/02 ,  H01L23/31 ,  H01L23/522 ,  H01G4/10 ,  H01L21/768 ,  H01G4/228

Abstract: The present disclosure provides a method for forming a semiconductor structure, including forming a bottom terminal, forming a first middle terminal over the bottom terminal, forming a top terminal over the first middle terminal, forming a first passivation layer over the top terminal, forming a first recess penetrating the first passivation layer and the bottom terminal by using a photomask, forming a dummy layer over the first passivation layer, forming an opening in the dummy layer and over the first recess, forming a conductive material in the first recess and the opening, and removing the dummy layer subsequent to forming the conductive material.

公开(公告)号：US20210035903A1

公开(公告)日：2021-02-04

申请号：US17074474

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor.

公开(公告)号：US20160086902A1

公开(公告)日：2016-03-24

申请号：US14495575

申请日：2014-09-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： GIA-HER LU ,  LIANG-CHEN LIN ,  TUNG-CHIN YEH ,  JYUN-LIN WU ,  TUNG-JIUN WU

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06181 ,  H01L2224/10126 ,  H01L2224/11002 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32106 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/92225 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2224/81805 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/11 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2221/68304 ,  H01L2224/83 ,  H01L21/56 ,  H01L21/304 ,  H01L2221/68368

Abstract: A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.

Abstract translation: 半导体封装结构包括半导体衬底，其包括从半导体衬底的第一表面延伸到第二表面的多个通过衬底通孔（TSV），其中第二表面与第一表面相对; 在第二表面上的多个导电凸块并连接到相应的TSV上; 在第二表面上的聚合物层并且围绕相应的导电凸块的下部。 聚合物层包括被构造为覆盖半导体衬底的外围区域的橡皮布的第一部分; 以及半导体衬底的芯区域中的第二部分，并且被配置为多个隔离带，其中每个隔离带围绕相应的导电凸块。

公开(公告)号：US20230253306A1

公开(公告)日：2023-08-10

申请号：US18303557

申请日：2023-04-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TUNG-JIUN WU

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L24/13 ,  H01L28/40 ,  H01L24/05 ,  H01L2924/19041 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05124 ,  H01L2224/05164 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2924/19104

Abstract: A semiconductor structure includes a substrate; a first dielectric layer disposed over the substrate; a conductive member surrounded by the first dielectric layer; a second dielectric layer disposed over the substrate, the first dielectric layer and the conductive member; a capacitor disposed over the conductive member and the second dielectric layer; a third dielectric layer disposed over the second dielectric layer and the capacitor; a conductive via disposed over and contacted with the conductive member, and extended through the second dielectric layer, the capacitor and the third dielectric layer; a conductive pad disposed over and contacted with the conductive via; a fourth dielectric layer disposed over the third dielectric layer and surrounding the conductive pad; and a conductive bump disposed over and electrically connected to the conductive pad, wherein the third dielectric layer includes an oxide layer and a nitride layer.