公开(公告)号：US20240121883A1

公开(公告)日：2024-04-11

申请号：US18543336

申请日：2023-12-18

Applicant: BorgWarner Inc.

Inventor： Lathom Alexander Louco

IPC: H05K1/02 ,  H05K5/00 ,  H05K7/20

CPC classification number: H05K1/0209 ,  H05K5/003 ,  H05K7/20845 ,  H05K2201/042 ,  H05K2201/10166 ,  H05K2201/10212

Abstract: An electronics assembly used in a vehicle included a printed circuit board (PCB) having a first side and a second side; a plurality of electrical components mounted on the first side of the PCB; a heat sink, configured to receive cooling fluid from a source, positioned adjacent to the second side of the PCB; and a cooling fluid conduit, configured to communicate the cooling fluid from a fluid inlet to a fluid outlet, wherein the cooling fluid conduit is positioned adjacent to the first side of the PCB and directly contacts an outer surface of the electrical components.

公开(公告)号：US11758645B2

公开(公告)日：2023-09-12

申请号：US17656432

申请日：2022-03-25

Applicant: Delta Electronics (Shanghai) CO., LTD

Inventor： Shouyu Hong ,  Qingdong Chen ,  Sansan Guo ,  Wulong Cong ,  Yiqing Ye ,  Chongfeng Zheng ,  Ganyu Zhou ,  Pengkai Ji

IPC: G06F1/26 ,  H05K1/14 ,  H05K1/02

CPC classification number: H05K1/0231 ,  G06F1/26 ,  H05K1/141 ,  H05K1/144 ,  H05K2201/10212

Abstract: The present disclosure provides a power supply system and an electronic device. The power supply system is used to supply power to a load and includes a system board where the load is disposed; a substrate; at least one output capacitor surface-mounted on the second side of the system board; at least one positive output conductive-connected region disposed on the first side of the substrate, and being electrically connected to one terminal of the at least one output capacitor; at least one negative output conductive-connected region disposed on the first side of the substrate, and being electrically connected to other terminal of the at least one output capacitor; and at least one power unit disposed on the second side of the substrate, and being electrically connected to the at least one positive output conductive-connected region and the at least one negative output conductive-connected region.

公开(公告)号：US11716814B2

公开(公告)日：2023-08-01

申请号：US17853854

申请日：2022-06-29

Applicant: Synaptics Incorporated

Inventor： Toshifumi Ogata ,  Atsushi Maruyama ,  Goro Sakamaki

IPC: H05K1/18 ,  G06F1/18 ,  H05K3/30

CPC classification number: H05K1/181 ,  G06F1/183 ,  H05K3/303 ,  H05K2201/10128 ,  H05K2201/10212 ,  H05K2203/166

Abstract: A display panel includes a plastic substrate and a first inner lead bonding (ILB) electrode on the plastic substrate. The first ILB electrode includes a first bonding segment, a second bonding segment, and a first connection segment. The first bonding segment is extended in a first direction oblique to a vertical direction of the display panel. The first connection segment is configured to provide an electrical connection between the first bonding segment and the second bonding segment. The first ILB electrode is configured to be bonded to an integrated circuit chip using one of the first bonding segment or the second bonding segment.

公开(公告)号：US09905303B2

公开(公告)日：2018-02-27

申请号：US15133217

申请日：2016-04-19

Applicant: Virident Systems, Inc.

Inventor： Ruban Kanapathippillai ,  Kenneth Alan Okin

IPC: G11C5/04 ,  G11C16/08 ,  G11C16/30 ,  G11C5/14 ,  H05K1/18 ,  H01R12/72 ,  H05K1/02

CPC classification number: G11C16/30 ,  G11C5/04 ,  G11C5/14 ,  G11C16/08 ,  H01R12/725 ,  H05K1/0286 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10212 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49169

Abstract: In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.

公开(公告)号：US09681543B2

公开(公告)日：2017-06-13

申请号：US15049363

申请日：2016-02-22

Applicant: HARRIS CORPORATION

Inventor： Louis Joseph Rendek, Jr. ,  Travis L. Kerby ,  Casey Philip Rodriguez ,  Michael Raymond Weatherspoon

IPC: H01L21/00 ,  H05K1/11 ,  H01L23/00 ,  H05K3/28 ,  H05K1/03 ,  H05K1/09 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81855 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/83359 ,  H01L2224/8388 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/181 ,  H05K3/287 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/0141 ,  H05K2201/10098 ,  H05K2201/10151 ,  H05K2201/10166 ,  H05K2201/10212 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.

公开(公告)号：US20170164482A1

公开(公告)日：2017-06-08

申请号：US15351234

申请日：2016-11-14

Applicant: The Board of Trustees of the University of Illinois

Inventor： John A. ROGERS ,  Seung-Kyun KANG ,  SukWon HWANG ,  Jianjun CHENG ,  Yanfeng ZHANG ,  Hanze YING

IPC: H05K1/18 ,  H05K3/28 ,  H05K1/03 ,  H01L25/065 ,  A61B5/00 ,  H01L23/29 ,  H01L23/498 ,  H01L21/56 ,  H01L21/02 ,  H01L21/311 ,  G06K19/077 ,  H01L23/31

CPC classification number: H05K1/185 ,  A61B5/686 ,  A61B2562/125 ,  A61M5/44 ,  G06K19/0775 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2924/0002 ,  H05K1/0275 ,  H05K1/0286 ,  H05K1/0306 ,  H05K3/22 ,  H05K3/285 ,  H05K3/287 ,  H05K3/288 ,  H05K5/069 ,  H05K13/00 ,  H05K2201/10151 ,  H05K2201/10196 ,  H05K2201/10212 ,  H05K2203/0271 ,  H05K2203/0292 ,  H05K2203/0769 ,  H05K2203/0776 ,  H05K2203/0786 ,  H05K2203/17 ,  H05K2203/175 ,  H05K2203/178 ,  Y10T29/49124 ,  Y10T137/0318 ,  Y10T428/239 ,  H01L2924/00

Abstract: The invention provides transient devices, including active and passive devices that physically, chemically and/or electrically transform upon application of at least one internal and/or external stimulus. Incorporation of degradable device components, degradable substrates and/or degradable encapsulating materials each having a programmable, controllable and/or selectable degradation rate provides a means of transforming the device. In some embodiments, for example, transient devices of the invention combine degradable high performance single crystalline inorganic materials with selectively removable substrates and/or encapsulants.

公开(公告)号：US09627110B2

公开(公告)日：2017-04-18

申请号：US14369599

申请日：2012-09-28

Applicant: Hiroshi Tamagawa ,  Yasuhiro Kondo

Inventor： Hiroshi Tamagawa ,  Yasuhiro Kondo

IPC: H01C10/50 ,  H01C17/00 ,  H01C17/23 ,  H05K3/34 ,  H01L27/01 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01C1/16 ,  H01C1/012 ,  H01C1/14 ,  H01C10/50 ,  H01C17/006 ,  H01C17/23 ,  H01L27/016 ,  H01L27/0207 ,  H01L28/24 ,  H05K3/3442 ,  H05K2201/10212 ,  Y02P70/613

Abstract: [Problem] There is demand for chip resistors that are compact and that have high resistivity. [Solution] A chip resistor (100) has a substrate (11), a first connection electrode (12) and a second connection electrode (13) that are formed on the substrate (11), and a resistor network that is formed on the substrate (11) and that has ends one of which is connected to the first connection electrode (12) and the other one of which is connected to the second connection electrode (13). The resistor network is provided with a resistive circuit. The resistive circuit has a resistive element film line (103) that is provided along inner wall surfaces of trenches (101). The resistive element film line (103) extending along the inner wall surfaces of the trenches (101) is long and has a high resistivity as a unit resistive element. [Effect] The resistivity of the chip resistor (100) as a whole can be increased.

公开(公告)号：US20160080333A1

公开(公告)日：2016-03-17

申请号：US14787848

申请日：2014-05-14

Applicant: NEC CORPORATION

Inventor： Toshiyuki ISSHIKI

IPC: H04L29/06 ,  H04L9/30

CPC classification number: G06F1/3212 ,  G06F3/00 ,  G06F13/40 ,  H01L23/5382 ,  H01L2924/0002 ,  H04L9/3093 ,  H04L63/0442 ,  H04L2209/24 ,  H05K1/029 ,  H05K1/142 ,  H05K2201/10037 ,  H05K2201/10212 ,  Y02D10/174 ,  H01L2924/00

Abstract: A collation system includes a first node, a second node and a third node. The first node includes: an encryption unit; a distance calculation unit t; and a collation data generation unit. The second node includes: a key generation unit; and a collation unit. The third node includes: a storage unit; and a collation information generation unit.

Abstract translation: 核对系统包括第一节点，第二节点和第三节点。 第一节点包括：加密单元; 距离计算单元t; 和核对数据生成单元。 第二节点包括：密钥生成单元; 和对照单元。 第三节点包括：存储单元; 和核对信息生成单元。

公开(公告)号：US09224432B2

公开(公告)日：2015-12-29

申请号：US14077656

申请日：2013-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Park

IPC: G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  H05K1/11 ,  H01L23/50 ,  H01L25/18 ,  H05K3/28 ,  H01L23/498

CPC classification number: G11C5/063 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49855 ,  H01L23/50 ,  H01L25/18 ,  H01L2224/10 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06568 ,  H05K1/113 ,  H05K3/284 ,  H05K2201/10212 ,  H01L2924/00014

Abstract: In a semiconductor package, a circuit pattern is arranged in a circuit board and contact pads on the circuit board are connected with the circuit pattern. Contact terminals contact external contact elements on a first surface of the circuit board. An integrated circuit (IC) chip structure is mounted on the circuit board and electrically connected to the inner circuit pattern. An operation controller on the circuit board controls operation of the semiconductor package according to the package users' individual choice.

Abstract translation: 在半导体封装中，电路图案布置在电路板中，并且电路板上的接触焊盘与电路图案相连。 接触端子接触电路板第一表面上的外部接触元件。 集成电路（IC）芯片结构安装在电路板上并电连接到内部电路图案。 电路板上的操作控制器根据用户的个人选择来控制半导体封装的操作。

公开(公告)号：US09211851B2

公开(公告)日：2015-12-15

申请号：US13966464

申请日：2013-08-14

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： Mario Kasper ,  Christian Steinert

IPC: B60R16/02 ,  H01R43/00 ,  H05K1/02 ,  H05K3/22 ,  H05K3/34

CPC classification number: B60R16/02 ,  H01R43/002 ,  H05K1/0268 ,  H05K1/0286 ,  H05K3/225 ,  H05K3/3421 ,  H05K2201/10151 ,  H05K2201/10212 ,  Y10T29/49117

Abstract: A method is provided for eliminating an electrical short circuit that can be caused by a filamentary tin crystal in an electronics assembly in particular of a motor vehicle. The method includes, but is not limited to providing the electronics assembly, that includes, but is not limited to electrical components with connectors and conductor paths for connecting the components. The components have configurable inputs and outputs. At least two of the inputs and outputs of the electrical components are configured so as to form an input connector and an output connector so that in the event of the electrical short circuit caused by the filamentary tin crystal, a short circuit current flows between the input connector and the output connector, which short circuit current is high enough to destroy the filamentary tin crystal.

Abstract translation: 提供一种用于消除特别是机动车辆的电子组件中可能由丝状锡晶体引起的电短路的方法。 该方法包括但不限于提供电子组件，其包括但不限于具有用于连接部件的连接器和导体路径的电气部件。 这些组件具有可配置的输入和输出。 电气部件的至少两个输入和输出被配置成形成输入连接器和输出连接器，使得在由丝状锡晶体引起的电短路的情况下，短路电流在输入端 连接器和输出连接器，短路电流足够高以破坏丝状锡晶体。