公开(公告)号：US09761513B2

公开(公告)日：2017-09-12

申请号：US14266261

申请日：2014-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chung Yee ,  Chun Hui Yu

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/10 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.

公开(公告)号：US20160336244A1

公开(公告)日：2016-11-17

申请号：US15219254

申请日：2016-07-25

Applicant: Renesas Electronics Corporation

Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US20160284570A1

公开(公告)日：2016-09-29

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/56 ,  H01L23/373 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/30604 ,  H01L2221/68381

Abstract: The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier, an etched flip chip die attached to a top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound having a high thermal conductivity improves thermal performance of the etched flip chip die.

Abstract translation: 本公开涉及具有增强的热性能的具有密封模具的半导体封装。 半导体封装包括载体，附着在载体的顶表面上的蚀刻倒装芯片模具，第一模具化合物和第二模具化合物。 蚀刻的倒装芯片芯片包括器件层，并且基本上不包括衬底。 第一模具化合物位于载体的顶表面上，围绕蚀刻的倒装芯片模具，并且延伸超过蚀刻的倒装芯片模具的顶表面，以形成空腔，蚀刻的倒装芯片裸片的顶表面露出 。 第二模具化合物填充空腔并与蚀刻的倒装芯片模具的顶表面接触。 具有高导热性的第二模具化合物改善了蚀刻的倒装芯片的热性能。

公开(公告)号：US20160284568A1

公开(公告)日：2016-09-29

申请号：US14959129

申请日：2015-12-04

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/30604 ,  H01L2221/68381

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract translation: 本公开涉及增强封装的倒装芯片的热性能。 根据示例性工艺，在载体的顶表面上附接多个倒装芯片管芯，并且在载体的顶表面上施加第一模具化合物以封装多个倒装芯片管芯。 将第一模具化合物减薄以暴露每个倒装芯片裸片的衬底，然后基本上蚀刻掉每个倒装芯片裸片的衬底，以提供在空腔底部具有暴露表面的蚀刻倒装芯片裸片。 接下来，施加具有高导热性的第二模具化合物以基本上填充每个空腔，并且第二模具化合物的顶表面被平坦化。 最后，封装的蚀刻倒装芯片芯片可以作为模块进行标记，分割和测试。

公开(公告)号：US20140237815A1

公开(公告)日：2014-08-28

申请号：US13848549

申请日：2013-03-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Wei-Chin Lau ,  Hai-Wah Lim

IPC: H01L21/673 ,  H01L21/50 ,  H01L21/68

CPC classification number: H01L21/68 ,  H01L23/16 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/10 ,  H01L2224/10155 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/0008 ,  H05K3/3436 ,  H05K2201/09145 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/0278 ,  H05K2203/167 ,  Y10T29/49124 ,  Y10T29/49133 ,  Y10T29/53178 ,  Y10T156/10 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatus for coupling a stiffener frame to a circuit board are disclosed. In one aspect, an apparatus for engaging a stiffener frame and a circuit board positioned in a fixture is provided. The stiffener frame includes an edge. The apparatus includes an alignment plate that has a shoulder to engage the edge of the stiffener frame. The alignment plate includes a first opening with a peripheral wall to restrain movement of a circuit board relative to the stiffener frame.

Abstract translation: 公开了用于将加强框架耦合到电路板的方法和装置。 一方面，提供一种用于接合加强框架和定位在固定装置中的电路板的装置。 加强框架包括边缘。 该装置包括对准板，该对准板具有与加强框架的边缘接合的肩部。 对准板包括具有周壁的第一开口，以限制电路板相对于加强框架的移动。

公开(公告)号：US07863636B2

公开(公告)日：2011-01-04

申请号：US11990235

申请日：2006-08-02

Applicant: Shin-ichi Sakata ,  Atsuyuki Mitani

Inventor： Shin-ichi Sakata ,  Atsuyuki Mitani

IPC: H01L33/00 ,  H01L21/00

CPC classification number: C04B35/01 ,  C04B35/117 ,  C04B35/44 ,  C04B35/58 ,  C04B35/653 ,  C04B2235/3217 ,  C04B2235/3222 ,  C04B2235/3225 ,  C04B2235/3229 ,  C04B2235/3286 ,  C04B2235/764 ,  C04B2235/80 ,  C04B2235/963 ,  C04B2235/9661 ,  C09K11/7774 ,  H01L33/501 ,  H01L2224/10 ,  H05B33/14

Abstract: A substrate for light-emitting diodes, obtained by stacking a single crystal layer to form a light-emitting diode element onto a ceramic composite layer for light conversion, the ceramic composite layer having been formed by a unidirectional solidification method so that the ceramic composite layer comprises a solidified body having formed therein at least two or more oxide phases selected from single metal oxides and complex metal oxides to be continuously and three-dimensionally entangled with each other, with each oxide phase having a single crystal orientation, wherein at least one oxide phase out of the oxide phases in the solidified body contains a metal element oxide capable of emitting fluorescence.

Abstract translation: 通过将单晶层堆叠以形成发光二极管元件到用于光转换的陶瓷复合层上而获得的发光二极管的基板，所述陶瓷复合层通过单向凝固法形成，使得陶瓷复合层 包括其中形成有至少两个以上选自单金属氧化物和复合金属氧化物的氧化物彼此连续地且三维地缠结的凝固体，每个氧化物相具有单晶取向，其中至少一种氧化物 凝固体中的氧化物相的相位含有能够发出荧光的金属元素氧化物。

公开(公告)号：US07824964B2

公开(公告)日：2010-11-02

申请号：US12412479

申请日：2009-03-27

Applicant: Kai-Chih Wang ,  Fang-Chang Liu

Inventor： Kai-Chih Wang ,  Fang-Chang Liu

IPC: H01L21/82

CPC classification number: H01L27/14618 ,  H01L2224/02371 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/10 ,  H01L2924/00014

Abstract: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.

Abstract translation: 光电器件的封装结构。 封装结构包括反向设置在第一衬底上的器件芯片，其包括第二衬底和第一和第二衬底之间的第一电介质层。 第一电介质层包括形成在第一电介质层的与第二衬底不重叠的角部中的焊盘，使得焊盘的表面和侧壁暴露。 金属层直接形成在焊盘的暴露表面上并覆盖第二基板。 保护层覆盖金属层，具有用于暴露第二基板上的金属层的一部分的开口。 焊球设置在开口中，电连接到金属层。 本发明还公开了一种制造该方法的方法。

公开(公告)号：US07633133B2

公开(公告)日：2009-12-15

申请号：US11639411

申请日：2006-12-15

Applicant: Takashi Noma ,  Kazuo Okada ,  Shinzo Ishibe ,  Katsuhiko Kitagawa ,  Yuichi Morita ,  Shigeki Otsuka ,  Hiroshi Yamada ,  Noboru Okubo ,  Hiroyuki Shinogi ,  Mitsuru Okigawa

Inventor： Takashi Noma ,  Kazuo Okada ,  Shinzo Ishibe ,  Katsuhiko Kitagawa ,  Yuichi Morita ,  Shigeki Otsuka ,  Hiroshi Yamada ,  Noboru Okubo ,  Hiroyuki Shinogi ,  Mitsuru Okigawa

IPC: H01L31/0203 ,  H01L31/0216 ,  H01L31/0224

CPC classification number: H01L27/14618 ,  H01L27/14636 ,  H01L31/0203 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10 ,  H01L2924/00014

Abstract: This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is formed on a front surface of a semiconductor substrate, and a plurality of ball-shaped conductive terminals is disposed on a back surface of the semiconductor substrate. Each of the conductive terminals is electrically connected to a pad electrode on the front surface of the semiconductor substrate through a wiring layer. The wiring layer and the conductive terminal are formed on the back surface of the semiconductor substrate except in a region overlapping the light receiving element in a vertical direction, and are not disposed in a region overlapping the light receiving element.

Abstract translation: 本发明提供一种半导体器件，其解决了形成在半导体衬底的背面上的布线的图案在输出图像上反射的问题。 在半导体衬底的前表面上形成有光接收元件（例如CCD，红外线传感器，CMOS传感器或照明传感器），并且多个球形导电端子设置在 半导体衬底。 每个导电端子通过布线层电连接到半导体衬底的前表面上的焊盘电极。 布线层和导电端子形成在除了在垂直方向上与光接收元件重叠的区域之外的半导体基板的背面上，并且不布置在与光接收元件重叠的区域中。

公开(公告)号：US20090166667A1

公开(公告)日：2009-07-02

申请号：US11990235

申请日：2006-08-02

Applicant: Shin-ichi Sakata ,  Atsuyuki Mitani

Inventor： Shin-ichi Sakata ,  Atsuyuki Mitani

IPC: H01L33/00 ,  B32B18/00 ,  B32B9/00

CPC classification number: C04B35/01 ,  C04B35/117 ,  C04B35/44 ,  C04B35/58 ,  C04B35/653 ,  C04B2235/3217 ,  C04B2235/3222 ,  C04B2235/3225 ,  C04B2235/3229 ,  C04B2235/3286 ,  C04B2235/764 ,  C04B2235/80 ,  C04B2235/963 ,  C04B2235/9661 ,  C09K11/7774 ,  H01L33/501 ,  H01L2224/10 ,  H05B33/14

Abstract: A substrate for light-emitting diodes, which uses no fluorescent powder, enables formation of a good light-emitting diode element, resulting in less deterioration, transmits light of the light-emitting diode element, emits light by utilizing a part of the transmitted light, and allows the transmitted light and newly emitted light to be mixed and emitted, is provided.The substrate for light-emitting diodes of the present invention is a substrate for light-emitting diodes, obtained by stacking a single crystal layer enabling to form a light-emitting diode element thereon and a ceramic composite layer for light conversion comprising a solidified body having formed therein at least two or more oxide phases selected from a single metal oxide and a complex metal oxide to be continuously and three-dimensionally entangled with each other, wherein at least one oxide phase out of oxide phases in the solidified body contains a metal element oxide capable of emitting fluorescence.

Abstract translation: 不使用荧光粉末的发光二极管的基板能够形成良好的发光二极管元件，导致较少的劣化，透过发光二极管元件的光，利用透射光的一部分发光 ，并且允许透射光和新发射的光被混合和发射。 本发明的发光二极管用基板是通过层叠能够在其上形成发光二极管元件的单晶层和用于光转换的陶瓷复合层而获得的发光二极管的基板，其包括具有 在其中形成至少两个或更多个选自单一金属氧化物和复合金属氧化物的氧化物相，以连续地和三维地缠结在一起，其中固化体中的氧化物相中的至少一个氧化物相含有金属元素 能够发射荧光的氧化物。

公开(公告)号：US20090001495A1

公开(公告)日：2009-01-01

申请号：US11822011

申请日：2007-06-29

Applicant: Jui-Ping Weng ,  Jang-Cheng Hsieh ,  Tzu-Han Lin ,  Pai-Chun Peter Zung

Inventor： Jui-Ping Weng ,  Jang-Cheng Hsieh ,  Tzu-Han Lin ,  Pai-Chun Peter Zung

IPC: H01L31/00 ,  H01L21/00

CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L2224/10

Abstract: The invention provides an image sensor package and method for fabricating the same. The image sensor package comprises a first substrate comprising a sensor device thereon and a hole therein. A bonding pad comprising a first opening is formed on an upper surface of the first substrate. A second substrate comprising a spacer element with a second opening therein is disposed on the first substrate. A conductive plug is formed in the hole and passes through the first and second openings to the second substrate to electrically contact with the bonding pad. A conductive layer is formed on a lower surface of the first substrate and electrically connects to the conductive plug. A solder ball is formed on the conductive layer and electrically connects to the bonding pad by the conductive plug. The image sensor package further comprises a second substrate bonding to the first substrate. The image sensor package is relatively less thick, thus, the dimensions thereof are relatively reduced.