SEMICONDUCTOR PACKAGES
    1.
    发明申请

    公开(公告)号:US20190237432A1

    公开(公告)日:2019-08-01

    申请号:US16377352

    申请日:2019-04-08

    Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.

    Light emitting diode lighting module
    2.
    发明授权
    Light emitting diode lighting module 有权
    发光二极管照明模块

    公开(公告)号:US08770806B2

    公开(公告)日:2014-07-08

    申请号:US13645056

    申请日:2012-10-04

    Abstract: A light emitting diode (LED) lighting module is provided including an LED array, and at least one of a diffusing portion and a reflecting portion. The LED array, equipped with at least one LED, may include a side wall which surrounds the at least one LED. The diffusing portion may be detachably coupled to the LED array and may include a diffusion plate which diffuses light emitted from the at least one LED The reflecting portion may be detachably coupled to one of the LED array and the diffusing portion and may reflect light emitted from the at least one LED. The LED array may be selectively coupled with the diffusing portion, the reflecting portion, or both the diffusing portion and the reflecting portion.

    Abstract translation: 提供了一种发光二极管(LED)照明模块,其包括LED阵列,以及漫射部分和反射部分中的至少一个。 配备有至少一个LED的LED阵列可以包括围绕至少一个LED的侧壁。 漫射部分可以可拆卸地耦合到LED阵列,并且可以包括漫射板,其漫射从至少一个LED发射的光。反射部分可以可拆卸地耦合到LED阵列和漫射部分中的一个,并且可以反射从 所述至少一个LED。 LED阵列可以选择性地与扩散部分,反射部分或扩散部分和反射部分耦合。

    Semiconductor package including stepwise stacked chips

    公开(公告)号:US10157883B2

    公开(公告)日:2018-12-18

    申请号:US15404090

    申请日:2017-01-11

    Abstract: A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.

    Semiconductor package
    8.
    发明授权

    公开(公告)号:US10658350B2

    公开(公告)日:2020-05-19

    申请号:US16137743

    申请日:2018-09-21

    Abstract: A semiconductor package including a substrate including an external terminal; a first semiconductor chip on the substrate and having a first and a second region; at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and at least one third semiconductor chip on the at least one second semiconductor chip, wherein the first semiconductor chip includes a first pad electrically connected to the at least one second semiconductor chip; a second pad electrically connected to the at least one third semiconductor chip; and a third pad electrically connected to the external terminal, the first pad is on the top surface of the first region, and at least one of the second pad and the third pad is on a top surface of the second region.

    Semiconductor packages
    10.
    发明授权

    公开(公告)号:US10741526B2

    公开(公告)日:2020-08-11

    申请号:US16377352

    申请日:2019-04-08

    Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.

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