公开(公告)号：US20130341785A1

公开(公告)日：2013-12-26

申请号：US13530835

申请日：2012-06-22

Applicant: Lei Fu ,  Xuefeng Zhang ,  Lihong Cao

Inventor： Lei Fu ,  Xuefeng Zhang ,  Lihong Cao

IPC: H01L23/498 ,  H01L21/50 ,  H01L21/28

CPC classification number: H01L23/3192 ,  H01L23/293 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03416 ,  H01L2224/0347 ,  H01L2224/03515 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16506 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/20755 ,  H01L2924/20754 ,  H01L2924/20753 ,  H01L2924/20752 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/20759 ,  H01L2924/00

Abstract: Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Abstract translation: 公开了用于保护半导体芯片中易碎介质层的方法和装置。 一方面，提供一种制造方法，其包括在半导体芯片的导体焊盘上形成第一聚合物层，其中导体焊盘具有第一横向尺寸。 在第一聚合物层上形成底部金属化结构并与导电垫欧姆接触。 底部喷涂金属化结构具有大于第一横向尺寸的第二横向尺寸。 在第一聚合物层上形成第二聚合物层，其中第一开口露出底部金属化结构的至少一部分。

公开(公告)号：US08609526B2

公开(公告)日：2013-12-17

申请号：US12842617

申请日：2010-07-23

Applicant: Chung-Shi Liu ,  Cheng-Chung Lin ,  Ming-Che Ho ,  Kuo Cheng Lin ,  Meng-Wei Chou

Inventor： Chung-Shi Liu ,  Cheng-Chung Lin ,  Ming-Che Ho ,  Kuo Cheng Lin ,  Meng-Wei Chou

IPC: H01L21/445 ,  H01L21/4757

CPC classification number: H01L24/05 ,  H01L21/0206 ,  H01L21/02068 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/81022 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.

Abstract translation: 形成集成电路结构的方法包括在晶片上形成含铜晶种层，并在含铜种子层的暴露表面上进行除氧步骤。 除氧步骤使用包括氟和氧的工艺气体进行。 然后使用含氮气体在含铜种子层的暴露表面上进行还原/吹扫步骤。 含铜层镀在含铜种子层上。

公开(公告)号：US20130313710A1

公开(公告)日：2013-11-28

申请号：US13478010

申请日：2012-05-22

Applicant: Yangyang Sun ,  Randall S. Parker ,  Jaspreet S. Gandhi ,  Jin Li

Inventor： Yangyang Sun ,  Randall S. Parker ,  Jaspreet S. Gandhi ,  Jin Li

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0362 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Some embodiments include semiconductor constructions. The constructions have an electrically conductive post extending through a semiconductor die. The post has an upper surface above a backside surface of the die, and has a sidewall surface extending between the backside surface and the upper surface. A photosensitive material is over the backside surface and along the sidewall surface. Electrically conductive material is directly against the upper surface of the post. The electrically conductive material is configured as a cap over the post. The cap has an edge that extends laterally outwardly beyond the post and encircles the post. An entirety of the edge is directly over the photosensitive material. Some embodiments include methods of forming semiconductor constructions having photosensitive material adjacent through-wafer interconnects, and having electrically conductive material caps over and directly against upper surfaces of the interconnects and directly against an upper surface of the photosensitive material.

Abstract translation: 一些实施例包括半导体结构。 这些结构具有延伸穿过半导体管芯的导电柱。 该柱在模具的背面上方具有上表面，并且具有在背面和上表面之间延伸的侧壁表面。 感光材料位于背面和侧壁表面之上。 导电材料直接抵靠柱的上表面。 导电材料被配置为柱上的盖。 盖具有横向向外延伸超过柱并且包围柱的边缘。 整个边缘直接在感光材料的上方。 一些实施例包括形成具有邻近晶片间互连的感光材料的半导体结构的方法，并且在导电材料的上表面上并且直接抵靠互连的上表面并且直接抵靠感光材料的上表面。

公开(公告)号：US08586472B2

公开(公告)日：2013-11-19

申请号：US12836151

申请日：2010-07-14

Applicant: Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

公开(公告)号：US08581420B2

公开(公告)日：2013-11-12

申请号：US13009377

申请日：2011-01-19

Applicant: Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Chih-Horng Chang

Inventor： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Chih-Horng Chang

IPC: H01L23/02

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/535 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03848 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2924/01046 ,  H01L2924/01039 ,  H01L2924/01016 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2224/034 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An under-bump metallization (UBM) structure in a semiconductor device includes a copper layer, a nickel layer, and a Cu—Ni—Sn intermetallic compound (IMC) layer between the copper layer and the nickel layer.

Abstract translation: 半导体器件中的凸起下金属化（UBM）结构包括在铜层和镍层之间的铜层，镍层和Cu-Ni-Sn金属间化合物（IMC）层。

公开(公告)号：US20130280904A1

公开(公告)日：2013-10-24

申请号：US13883231

申请日：2011-10-18

Applicant: Lei Shi ,  Guohua Gao ,  Yujuan Tao ,  Naomi Masuda ,  Koichi Meguro

Inventor： Lei Shi ,  Guohua Gao ,  Yujuan Tao ,  Naomi Masuda ,  Koichi Meguro

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3178 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.

Abstract translation: 提供了一种芯片封装的方法，包括以下步骤：提供具有切割轨迹的半封装晶片和芯片的金属焊盘; 在切割道上形成第一保护层; 在金属焊盘上形成子球金属电极; 在子球金属电极上形成焊球; 沿着切割线切割晶片。 根据本发明的第一保护层可以防止切割轨迹中的金属通过电镀分离，并且在切割之后保护离散芯片的侧面。 其工艺流程简单，并且提高了包装的效率以及其收率。

公开(公告)号：US20130234319A1

公开(公告)日：2013-09-12

申请号：US13418113

申请日：2012-03-12

Applicant: Jaspreet S. Gandhi

Inventor： Jaspreet S. Gandhi

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

Abstract translation: 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：US08519516B1

公开(公告)日：2013-08-27

申请号：US13418113

申请日：2012-03-12

Applicant: Jaspreet S. Gandhi

Inventor： Jaspreet S. Gandhi

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

Abstract translation: 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：US20130213702A1

公开(公告)日：2013-08-22

申请号：US13852663

申请日：2013-03-28

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05547 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05578 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05687 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/301 ,  H01L2924/384 ,  Y10T428/12396 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/058 ,  H01L2224/05552

Abstract: A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.

Abstract translation: 凸起工艺包括在基底上形成具有铜的金属层的步骤，并且具有铜的金属层包括多个第一区域和第二区域; 用铜在金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口; 在所述开口内形成多个铜凸块，每个所述铜凸块覆盖所述第一区域并且包括第一顶表面; 在所述第一顶表面上形成连接层; 去除光致抗蚀剂层; 去除所述第二区域并且使得所述第一区域中的每一个形成凸起下冶金层，其中所述凸起下的冶金层，所述铜凸块和所述连接层具有其对应的周壁，以及覆盖在第一区上形成的第一保护层的覆盖部分 连接层可以覆盖那些外围壁以防止电离现象。

公开(公告)号：US20130181346A1

公开(公告)日：2013-07-18

申请号：US13743844

申请日：2013-01-17

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Yie-Chuan Chiu ,  Lung-Hua Ho

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11472 ,  H01L2224/1182 ,  H01L2224/11906 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/05552

Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.

Abstract translation: 凸起工艺包括提供硅衬底，在硅衬底上形成含钛金属层，其中含钛金属层包括多个第一区域和多个第二区域，在含钛金属层上形成光致抗蚀剂层 金属层，图案化光致抗蚀剂层以形成多个开口槽，在开口槽处形成多个底部覆盖层，进行热过程，形成多个外部覆盖层，以使每个外部覆盖层与每个 的底部覆盖层，其中所述外部覆盖层和所述底部覆盖层形成包裹层并且完全围绕铜凸块，在外部覆盖层上形成多个连接层，去除光致抗蚀剂层，去除第二区域并使能 每个第一区域形成凸块下的冶金层。