公开(公告)号：US20180174654A1

公开(公告)日：2018-06-21

申请号：US15893625

申请日：2018-02-10

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  G11C16/02 ,  G11C16/04 ,  H01L29/792 ,  H01L27/108 ,  G11C11/56 ,  H01L29/78

CPC classification number: G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

公开(公告)号：US09928910B2

公开(公告)日：2018-03-27

申请号：US15480677

申请日：2017-04-06

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  G11C11/56 ,  H01L27/108 ,  H01L29/78 ,  H01L29/792 ,  G11C16/04 ,  G11C16/02

CPC classification number: G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

公开(公告)号：US09922709B2

公开(公告)日：2018-03-20

申请号：US14715566

申请日：2015-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: G11C16/02 ,  G11C13/00 ,  G06F11/10 ,  H01L27/24 ,  H01L29/786 ,  H01L45/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

公开(公告)号：US20180047730A1

公开(公告)日：2018-02-15

申请号：US15728797

申请日：2017-10-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Keitaro IMAI ,  Jun KOYAMA

IPC: H01L27/108 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/06 ,  G11C11/404 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

公开(公告)号：US09806079B2

公开(公告)日：2017-10-31

申请号：US14950624

申请日：2015-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Keitaro Imai ,  Jun Koyama

IPC: H01L29/10 ,  H01L27/108 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/786 ,  H01L27/092

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

公开(公告)号：US09692421B2

公开(公告)日：2017-06-27

申请号：US13667292

申请日：2012-11-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H01L25/00 ,  H03K19/00 ,  H03K19/173 ,  G11C14/00 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H03K3/356 ,  G11C16/02 ,  H01L27/1156

CPC classification number: H03K19/1733 ,  G11C14/0063 ,  G11C16/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/356008 ,  H03K3/35606

Abstract: A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

公开(公告)号：US09659653B2

公开(公告)日：2017-05-23

申请号：US13772407

申请日：2013-02-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Saito

IPC: G11C11/24 ,  G11C16/02 ,  G11C11/404 ,  H01L29/94

CPC classification number: G11C16/02 ,  G11C11/404 ,  H01L29/94

Abstract: An object is to provide a semiconductor device capable of accurate data retention even with a memory element including a depletion mode transistor. A gate terminal of a transistor for controlling input of a signal to a signal holding portion is negatively charged in advance. The connection to a power supply is physically broken, whereby negative charge is held at the gate terminal. Further, a capacitor having terminals one of which is electrically connected to the gate terminal of the transistor is provided, and thus switching operation of the transistor is controlled with the capacitor.

公开(公告)号：US09524794B1

公开(公告)日：2016-12-20

申请号：US14822450

申请日：2015-08-10

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Ofer Shapira

IPC: G11C16/02 ,  G11C16/34 ,  G06F12/02

CPC classification number: G11C16/3495 ,  G06F12/0246 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/349

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to determine a first shaping level corresponding to applying a first shaping operation to data to be stored to the non-volatile memory. The controller is further configured to, in response to the first shaping level exceeding a threshold, perform a second shaping operation to generate shaped data that corresponds to the data, the shaped data having a second shaping level that is less than the threshold.

Abstract translation: 一种设备包括非易失性存储器和耦合到非易失性存储器的控制器。 控制器被配置为确定对应于对要被存储到非易失性存储器的数据应用第一整形操作的第一整形级别。 控制器还被配置为响应于第一整形级别超过阈值，执行第二整形操作以生成对应于数据的成形数据，成形数据具有小于阈值的第二整形级别。

公开(公告)号：US09336858B2

公开(公告)日：2016-05-10

申请号：US14460399

申请日：2014-08-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/404 ,  G11C16/02 ,  H01L21/28 ,  H01L27/115 ,  H01L27/105 ,  G11C16/04 ,  H01L49/02

CPC classification number: G11C11/4096 ,  G11C11/24 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/1156 ,  H01L28/40

Abstract: A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.

公开(公告)号：US09171625B2

公开(公告)日：2015-10-27

申请号：US13525035

申请日：2012-06-15

Applicant: Koji Sakui ,  Peter Sean Feeley

Inventor： Koji Sakui ,  Peter Sean Feeley

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/04 ,  G11C16/02

CPC classification number: G11C16/10 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0483

Abstract: Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.

Abstract translation: 公开了诸如包括多个电荷存储装置串的块的每个串，包括与柱相关联的多个电荷存储装置，并且每个支柱包括半导体材料。 公开了一种方法，例如包括在与块中的柱相关联的第一电荷存储装置上执行第一操作的方法，修改支柱的电位，以及对块中的第二电荷存储装置执行第二操作 。 描述附加的装置和方法。