公开(公告)号：US09345126B2

公开(公告)日：2016-05-17

申请号：US14198718

申请日：2014-03-06

申请人： CANON KABUSHIKI KAISHA

发明人： Sou Hoshi ,  Nobuaki Yamashita ,  Yusuke Murai

IPC分类号： H01L23/02 ,  H05K1/02 ,  H01L23/50 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H05K1/16 ,  H05K3/46

CPC分类号： H05K1/0224 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4644 ,  H05K2201/09263 ,  H05K2201/09672 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00

摘要： A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.

摘要翻译： 半导体封装的衬底包括形成在表面层中的导体图案，并且电连接到半导体元件的电源端子和接地端子之外的一个端子。 基板还在表面层中包括布置成与导体图案分离的导体图案，以及形成为具有比导体图案的布线宽度更薄的布线宽度的导体图案，并将导体图案与 导体图案。 衬底还包括形成在内层中的导体图案，其通过电介质面对导体图案，并且与另一个端子电连接到电源端子和半导体元件的接地端子之外。

公开(公告)号：US09343451B2

公开(公告)日：2016-05-17

申请号：US14685145

申请日：2015-04-13

申请人： Renesas Electronics Corporation

发明人： Katsuhiko Funatsu ,  Tomoaki Uno ,  Toru Ueguri ,  Yukihiro Sato

IPC分类号： H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/683 ,  H01L21/78 ,  H01L25/18 ,  H01L21/48

CPC分类号： H01L25/50 ,  H01L21/4835 ,  H01L21/4839 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

公开(公告)号：US20160133373A1

公开(公告)日：2016-05-12

申请号：US14536103

申请日：2014-11-07

申请人： Solantro Semiconductor Corp.

发明人： Raymond Kenneth Orr ,  James Benson Bacque ,  Mark Roy Harris

IPC分类号： H01F27/28 ,  H01F27/30 ,  H01L21/48 ,  H01F27/29 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01F27/2804 ,  H01F27/2852 ,  H01F27/29 ,  H01F27/303 ,  H01F2027/2819 ,  H01L21/4842 ,  H01L23/495 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49544 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/48177 ,  H01L2924/00014 ,  H01L2924/1711 ,  H01L2924/1715 ,  H01L2924/173 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45099

摘要： The present disclosure relates to non-planar inductive electrical elements in semiconductor package lead frames. A non-planar inductive element is formed from a lead frame in a semiconductor package. The semiconductor package also includes at least one semiconductor die coupled to the lead frame. The non-planar inductive element could be formed by deforming portions of a patterned planar lead frame blank to form the non-planar inductive element in a deformed lead frame blank. The deformed lead frame blank and the at least one semiconductor die could then be packaged into a semiconductor package. A setting tool could be used to deform the lead frame blank. A configurable lead frame blank could be configurable into any of a variety of inductive elements, through interconnection of lead frame segments using wire bonds, for example.

摘要翻译： 本公开涉及半导体封装引线框架中的非平面感应电元件。 非平面感应元件由半导体封装中的引线框形成。 半导体封装还包括耦合到引线框架的至少一个半导体管芯。 可以通过使图案化的平面引线框架坯件的部分变形以在变形的引线框架坯件中形成非平面感应元件来形成非平面感应元件。 然后可以将变形的引线框架坯件和至少一个半导体管芯封装成半导体封装。 可以使用设置工具使引线框架空白变形。 例如，通过使用引线键的引线框架段的互连，可配置的引线框架空白可以被配置成各种电感元件中的任何一个。

公开(公告)号：US09318448B2

公开(公告)日：2016-04-19

申请号：US14401132

申请日：2012-05-30

申请人： Patrice Besse ,  Kamel Abouda ,  Valerie Bernon-Enjalbert ,  Philippe Givelin

发明人： Patrice Besse ,  Kamel Abouda ,  Valerie Bernon-Enjalbert ,  Philippe Givelin

IPC分类号： H01L23/60 ,  H01L27/02 ,  H01L21/761 ,  H01L21/762 ,  H01L27/04 ,  H01L29/74

CPC分类号： H01L23/60 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0262 ,  H01L27/04 ,  H01L29/74 ,  H01L29/7436 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/13034 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region. At least part of the second P-type region is arranged in between the first semiconductor component and the second semiconductor component, and at least part of the third N-type region is arranged in between the at least part of the first P-type region and the second semiconductor component.

摘要翻译： 描述了包括封装和半导体器件的封装半导体器件。 半导体器件包括分别与第一和第二接合线接合到一个或多个GND引脚的第一和第二GND焊盘，用第三接合线接合到第一功能引脚的第一功能焊盘，半导体层 P型导电性，第一半导体元件和第二半导体元件。 第一半导体部件被布置成当瞬态电流被施加到第一功能引脚时，至少一部分瞬态电流从第一P区转移到第一GND焊盘，至少一个 第一PN结。 第二半导体部件包括与第一功能焊盘相关联的第二半导体部件的端子的第二N型区域。 第一GND焊盘与第二P型区域接触。 第二GND焊盘与第三N型区域接触。 第二P型区域的至少一部分配置在第一半导体部件和第二半导体部件之间，第三N型区域的至少一部分配置在第一P型区域的至少一部分之间 和第二半导体部件。

公开(公告)号：US09312245B2

公开(公告)日：2016-04-12

申请号：US14496140

申请日：2014-09-25

申请人： International Rectifier Corporation

发明人： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC分类号： H01L25/07 ,  H01L27/20 ,  H01L23/495 ,  H01L29/20 ,  H01L29/16 ,  H01L29/772 ,  H01L23/00 ,  H01L29/778

CPC分类号： H01L25/074 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/69 ,  H01L24/72 ,  H01L24/73 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/772 ,  H01L29/778 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

摘要翻译： 一个示例性的公开的实施例包括三端子堆叠管芯封装，其包括层叠在III族氮化物晶体管的顶部的诸如硅PET的场效应晶体管（PET），使得PET的漏极位于电耦合到 III族氮化物晶体管的源极。 封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。 封装的第三端子耦合到FET的源极。 以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

公开(公告)号：US09307666B2

公开(公告)日：2016-04-05

申请号：US14261626

申请日：2014-04-25

申请人： Hitachi, Ltd.

发明人： Takeshi Tokuyama ,  Kinya Nakatsu ,  Atushi Kawabata

IPC分类号： H05K7/20 ,  H05K7/02 ,  H02M7/00

CPC分类号： H05K7/02 ,  H01G2/08 ,  H01G4/224 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H02M7/003 ,  Y02T10/7022 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.

摘要翻译： 本发明提供一种电路装置，其中可以同时实现冷却性能的提高和由于线路电感引起的工作损耗的降低。 上述目的可以通过构造多个板状导体来实现，使得电连接到多个半导体芯片的这些导体中的每一个也热连接到每个这样的半导体芯片的两个芯片表面，以从每个半导体芯片的芯片表面释放热量， 并且使得在上述导体中，DC正极板状导体和DC负极板状导体在各导体表面处彼此相对。

公开(公告)号：US09295157B2

公开(公告)日：2016-03-22

申请号：US13939066

申请日：2013-07-10

申请人： Skyworks Solutions, Inc.

发明人： Howard E. Chen ,  Matthew Sean Read ,  Hoang Mong Nguyen ,  Anthony James LoBianco ,  Guohao Zhang ,  Dinhphuoc Vu Hoang

IPC分类号： H05K7/00 ,  H05K1/18 ,  G06F17/50 ,  H01L23/552 ,  H01L21/56 ,  H01L23/00

CPC分类号： G06F17/5072 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Aspects of the present disclosure relate to determining a layout of a racetrack that forms part of an RF isolation structure of a packaged module and the resulting RF isolation structures. Locations of where the racetrack can be adjusted (for example, narrowed) and/or removed without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, a portion of the racetrack can be removed to create a break and/or a portion of the racetrack can be narrowed in a selected area.

摘要翻译： 本公开的方面涉及确定构成封装模块的RF隔离结构的一部分的跑道的布局以及所得到的RF隔离结构。 可以识别可以调整（例如，变窄）和/或移除赛道的位置，而不会显着降低RF隔离结构的EMI性能。 在某些实施例中，可以移除跑道的一部分以产生断路，和/或可以在选定的区域中使跑道的一部分变窄。

公开(公告)号：US09275946B2

公开(公告)日：2016-03-01

申请号：US14629227

申请日：2015-02-23

申请人： Power Integrations, Inc.

发明人： Balu Balakrishnan ,  David Michael Hugh Matthews

IPC分类号： H01L23/495 ,  H02M3/00 ,  H01L23/48 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H02M3/335

CPC分类号： H01L23/49575 ,  H01L23/48 ,  H01L23/495 ,  H01L23/49541 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/29099 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H02M3/00 ,  H02M3/33523 ,  H01L2924/00 ,  H01L2224/45099

摘要： An integrated circuit package for use in a switch mode power converter includes a portion of a lead frame disposed within an encapsulation. The lead frame includes a first conductor having an inner conductive loop disposed within the encapsulation, and a second conductor galvanically isolated from the first conductor having an outer conductive loop disposed within the encapsulation and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductors. First and second control circuits are coupled to the first and second conductors, respectively. The first control circuit is coupled to control a switching circuit in response to one or more control signals communicated between first and second dice that include the first and second control circuits, respectively, through the communication link to regulate a transfer of energy from an input to an output of the switch mode power converter.

摘要翻译： 用于开关模式功率转换器的集成电路封装包括布置在封装内的引线框架的一部分。 引线框架包括具有设置在封装内的内部导电回路的第一导体，以及与第一导体电隔离的第二导体，其具有布置在封装内的外部导电环，并且磁耦合到第一导电环，以提供 第一和第二导体。 第一和第二控制电路分别耦合到第一和第二导体。 第一控制电路被耦合以响应于通过通信链路分别在包括第一和第二控制电路的第一和第二骰子之间传送的一个或多个控制信号来控制开关电路，以调节能量从输入到 开关模式电源转换器的输出。

公开(公告)号：US20160056084A1

公开(公告)日：2016-02-25

申请号：US14930123

申请日：2015-11-02

申请人： Estivation Properties LLC

发明人： Robert Bruce Davies

IPC分类号： H01L21/8234 ,  H01L23/552 ,  H01L21/768

CPC分类号： H01L27/0296 ,  H01L21/2815 ,  H01L21/32055 ,  H01L21/56 ,  H01L21/76224 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L23/047 ,  H01L23/051 ,  H01L23/10 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4824 ,  H01L23/49844 ,  H01L23/552 ,  H01L23/66 ,  H01L24/06 ,  H01L24/83 ,  H01L25/50 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7817 ,  H01L2223/6644 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

公开(公告)号：US09263411B2

公开(公告)日：2016-02-16

申请号：US14406964

申请日：2013-07-05

申请人： Advanced Photonics, Inc.

发明人： Xueliang Song ,  Nozomu Sato ,  Genta Kanno ,  Yohko Makino

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/03 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/03334 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/13144 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1714 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48496 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48766 ,  H01L2224/48769 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48866 ,  H01L2224/48869 ,  H01L2224/48997 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/85395 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/85466 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/03 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/48455 ,  H01L2924/00012 ,  H01L2224/4554

摘要： The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps, are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount.

摘要翻译： 本发明提供了一种包括半导体元件并且可以容易地连接到主基板上的IC的基座。 本发明的一个实施例中的基座包括：基板; 电极 半导体元件; 金线; 和金块。 电极，半导体元件，Au线和金凸块通过树脂封装在基板上。 通过球接合在电极和Au线上形成金凸块，并通过切割来切割金凸块的侧表面。 暴露的表面用作副安装座的侧面电极。