公开(公告)号：US09450283B2

公开(公告)日：2016-09-20

申请号：US11722521

申请日：2005-12-15

申请人： Igor Blednov

发明人： Igor Blednov

IPC分类号： H01B1/04 ,  H01P5/18 ,  H01L23/66 ,  H03H7/38 ,  H03H7/48 ,  H04W52/52 ,  H01L23/00

CPC分类号： H01P5/18 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03H7/383 ,  H03H7/48 ,  H04W52/52 ,  H01L2924/00014 ,  H01L2924/00

摘要： An RF power device that includes a transistor with a compact impedance transformation circuit, where the transformation circuit includes a lumped element CLC analog transmission line and an associated embedded directional bilateral RF power sensor that is inductively coupled to the transmission line to provide detection of direct and reflected power independently with high directivity.

摘要翻译： 一种RF功率器件，其包括具有紧凑型阻抗变换电路的晶体管，其中所述变换电路包括集总元件CLC模拟传输线和相关联的嵌入式定向双向RF功率传感器，其被感应耦合到所述传输线以提供直接和 反射功率独立，方向性高。

公开(公告)号：US20160260646A1

公开(公告)日：2016-09-08

申请号：US15153433

申请日：2016-05-12

申请人： STATS ChipPAC Pte. Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

公开(公告)号：US09425158B2

公开(公告)日：2016-08-23

申请号：US12652399

申请日：2010-01-05

申请人： Antti Iihola ,  Tuomas Waris

发明人： Antti Iihola ,  Tuomas Waris

IPC分类号： H05K1/00 ,  H01L23/00 ,  H05K1/18 ,  H05K3/46

CPC分类号： H05K1/028 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/182 ,  H05K1/188 ,  H05K1/189 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09127 ,  H05K2203/308 ,  H01L2924/0665 ,  H01L2924/00

摘要： Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane (20) and a sacrificial-material piece (16) are attached to an insulator membrane (12) in the location of the flexible zone (13). An insulator layer (1), which encloses within itself a sacrificial-material piece (16) is manufactured on the surface of the conductor membrane (12). The flexible zone (13) is formed in such a way that an opening (9) is made in the insulator layer (1), through which the sacrificial-material piece (16) is removed. The flexible zone comprises at least part of the flexible membrane (20) as well as conductors (22), which are manufactured by patterning the insulator membrane (12) at a suitable stage in the method.

摘要翻译： 柔性柔性电路板结构和制造方法，其中柔性膜（20）和牺牲材料片（16）在柔性区（13）的位置附接到绝缘膜（12）。 在导体膜（12）的表面上制造绝缘体层（1），其内包封牺牲材料片（16）。 柔性区域（13）形成为在绝缘体层（1）中形成开口（9），去除牺牲材料片（16）。 柔性区域包括柔性膜（20）的至少一部分以及通过在该方法中的合适阶段对绝缘膜（12）进行图案化而制造的导体（22）。

公开(公告)号：US09418913B2

公开(公告)日：2016-08-16

申请号：US13682510

申请日：2012-11-20

申请人： STATS ChipPAC, Ltd.

发明人： Seong Bo Shim ,  Kyung Oe Kim ,  Yong Hee Kang

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H01L21/50 ,  H01L23/482 ,  H01L25/10

CPC分类号： H01L23/48 ,  H01L21/4846 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3452 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate.

摘要翻译： 半导体器件具有在半导体管芯的有效表面上形成有多个凸点的半导体管芯。 具有互连位置的多个第一导电迹线形成在衬底上。 凸块比互连部位宽。 在第一导电迹线上形成表面处理。 与第一导电迹线相邻地形成多个第二导电迹线。 在第二导电迹线上形成氧化物层。 在衬底的远离互连位置的区域上形成掩模层。 这些凸块被结合到互连部位，使得凸块覆盖互连部位的顶表面和侧表面。 氧化物层保持凸块和第二导电迹线之间的电隔离。 在半导体管芯和衬底之间的凸起周围沉积密封剂。

公开(公告)号：US20160218088A1

公开(公告)日：2016-07-28

申请号：US15086693

申请日：2016-03-31

申请人： Invensas Corporation

发明人： Simon J. S. McElrea ,  Marc E. Robinson ,  Lawrence Douglas Andrews, JR.

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L23/48 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L29/0657 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/00

摘要： Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

摘要翻译： 堆叠的模具组件电连接到任何支撑件上的连接部位，而不与任何插入的基板或引线框架电连接，并且没有焊料。

公开(公告)号：US20160197254A1

公开(公告)日：2016-07-07

申请号：US15067995

申请日：2016-03-11

申请人： LG INNOTEK CO., LTD.

发明人： Yeo Chan YOON ,  Jae Hwan Jung ,  Yun Shick Eom ,  Ki Rok Hur ,  Jin Seong Kim

IPC分类号： H01L33/62 ,  H01L33/52

CPC分类号： H01L33/62 ,  H01L25/167 ,  H01L33/486 ,  H01L33/52 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01015

摘要： Disclosed are a light emitting device and a lighting system having the same. The light emitting device includes a body including first and second lateral side parts, third and fourth lateral side parts, and a cavity, a first lead frame extending in a direction of the first lateral side part of the body, a second lead frame extending in a direction of the second lateral side part of the body, a light emitting chip disposed on the first lead frame in the cavity, and a gap part between the first and second lead frames. The first lead frame includes a first recess part having a first depth, and a second recess part recessed at a second depth, and the first recess part and the second recess part have a step structure with a curved surface.

摘要翻译： 公开了一种发光器件和具有该发光器件的照明系统。 发光装置包括主体，该主体包括第一和第二横向侧部，第三和第四横向侧部，以及空腔，沿主体的第一横向侧部分的方向延伸的第一引线框架， 主体的第二横向侧部分的方向，设置在空腔中的第一引线框架上的发光芯片以及第一引线框架和第二引线框架之间的间隙部分。 第一引线框架包括具有第一深度的第一凹部和在第二深度上凹陷的第二凹部，第一凹部和第二凹部具有带弯曲表面的台阶结构。

公开(公告)号：US09362141B2

公开(公告)日：2016-06-07

申请号：US13898004

申请日：2013-05-20

申请人： Micron Technology, Inc.

发明人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC分类号： H01L21/58 ,  H01L21/56 ,  H01L25/065 ,  H01L25/11 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/66

CPC分类号： H01L23/053 ,  H01L21/56 ,  H01L21/561 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

公开(公告)号：US20160148885A1

公开(公告)日：2016-05-26

申请号：US14899378

申请日：2013-06-19

申请人： SENJU METAL INDUSTRY CO., LTD.

发明人： Hiroyoshi Kawasaki ,  Tomohiko Hashimoto ,  Atsushi Ikeda ,  Takahiro Roppongi ,  Daisuke Soma ,  Isamu Sato ,  Yuji Kawamata

IPC分类号： H01L23/00 ,  C22C13/00 ,  C22C9/00 ,  H05K3/34 ,  B23K35/02 ,  B23K35/30 ,  B23K35/26 ,  H01L23/498 ,  C22C43/00

CPC分类号： H01L24/13 ,  B22F1/025 ,  B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/30 ,  B23K35/302 ,  C22C9/00 ,  C22C13/00 ,  C22C43/00 ,  C23C28/021 ,  H01L23/49816 ,  H01L23/556 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/111 ,  H01L2224/1112 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13347 ,  H01L2224/13411 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/1434 ,  H01L2924/3841 ,  H05K3/3457 ,  H05K2203/041 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01051 ,  H01L2924/01032 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/01079 ,  H01L2924/01092 ,  H01L2924/0109 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01048 ,  H01L2924/01016 ,  H01L2924/01203 ,  H01L2924/01204 ,  H01L2924/0103

摘要： A Cu core ball is provided that prevents any soft errors and decreases any connection failure. The Cu core ball includes a solder plating film formed on the surface of a Cu ball that is a Sn solder plating film or is made of a lead-free solder alloy, a principal ingredient of which is Sn. The solder plating film contains U of 5 ppb or less and Th of 5 ppb or less. The Cu ball has a purity of not less than 99.9% Cu and not more than 99.995% Cu. Pb and/or Bi contents therein are at a total of 1 ppm or more. The sphericity thereof is 0.95 or more. The obtained Cu core ball has an α dose of 0.0200 cph/cm2 or less.

摘要翻译： 提供铜芯球，防止任何软错误并减少任何连接故障。 铜芯球包括在作为Sn焊料镀覆膜的Cu球的表面上形成的焊锡镀膜，或者由主要成分为Sn的无铅焊料合金制成。 焊锡镀膜含有5ppb以下的U，5ppb以下的U。 Cu球的纯度为99.9％以上，Cu不大于99.995％。 其中Pb和/或Bi含量总共为1ppm以上。 其球形度为0.95以上。 得到的Cu芯球的α剂量为0.0200cph / cm 2以下。

公开(公告)号：US20160142011A1

公开(公告)日：2016-05-19

申请号：US14943836

申请日：2015-11-17

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Toshiaki TSUTSUMI ,  Yoshihiro FUNATO ,  Tomonori OKUDAIRA ,  Tadato YAMAGATA ,  Akihisa UCHIDA ,  Takeshi TERASAKI ,  Tomohisa SUZUKI ,  Yoshiharu KANEGAE

IPC分类号： H03B5/24 ,  H01L49/02 ,  H01L23/00 ,  H01L23/31

CPC分类号： H03B5/24 ,  H01L23/3107 ,  H01L23/5228 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554 ,  H01L2224/06179 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01015 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H03L7/24 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.

公开(公告)号：US09331149B2

公开(公告)日：2016-05-03

申请号：US14754111

申请日：2015-06-29

申请人： Ziptronix, Inc.

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, Jr. ,  Paul M. Enquist

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L29/16 ,  H01L21/02 ,  H01L21/20 ,  H01L21/311 ,  H01L21/762 ,  H01L23/00 ,  H01L29/06 ,  H01L21/322 ,  H01L27/085

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.