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公开(公告)号:US20180323797A1
公开(公告)日:2018-11-08
申请号:US16031872
申请日:2018-07-10
发明人: Kazuaki KUROOKA , Yoshihiro FUNATO
CPC分类号: H03M1/485 , H03M1/0872 , H03M1/645
摘要: In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
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公开(公告)号:US20170205458A1
公开(公告)日:2017-07-20
申请号:US15402660
申请日:2017-01-10
CPC分类号: G01R31/025 , G01D5/12 , G01D5/24466 , H02H7/0833 , H02P6/12 , H03F3/45071 , H03F3/45475 , H03F2200/129 , H03F2200/231 , H03F2200/234 , H03F2200/261 , H03F2203/45116 , H03F2203/45138 , H03F2203/45171 , H03F2203/45528 , H03K3/017
摘要: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.
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公开(公告)号:US20160142011A1
公开(公告)日:2016-05-19
申请号:US14943836
申请日:2015-11-17
发明人: Toshiaki TSUTSUMI , Yoshihiro FUNATO , Tomonori OKUDAIRA , Tadato YAMAGATA , Akihisa UCHIDA , Takeshi TERASAKI , Tomohisa SUZUKI , Yoshiharu KANEGAE
CPC分类号: H03B5/24 , H01L23/3107 , H01L23/5228 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/0629 , H01L28/20 , H01L28/24 , H01L2224/05554 , H01L2224/06179 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2924/01015 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H03L7/24 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.
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公开(公告)号:US20180054212A1
公开(公告)日:2018-02-22
申请号:US15797150
申请日:2017-10-30
发明人: Yoshihiro FUNATO , Yasuo MORIMOTO
CPC分类号: H03M1/466 , H03M1/06 , H03M1/0695 , H03M1/468
摘要: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
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公开(公告)号:US20170194979A1
公开(公告)日:2017-07-06
申请号:US15371101
申请日:2016-12-06
CPC分类号: H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
摘要: During a period of calibration of the ADC, the effect of unexpected external noise can be excluded.Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.
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公开(公告)号:US20230343700A1
公开(公告)日:2023-10-26
申请号:US18163566
申请日:2023-02-02
IPC分类号: H01L23/522 , H01L23/532 , H01L25/065
CPC分类号: H01L23/5228 , H01L23/5329 , H01L25/0655 , H01L2924/14253 , H01L2924/142
摘要: A semiconductor device includes a plurality of resistive films arranged on an interlayer dielectric film. Each of the plurality of resistive films extends in a first direction in plan view. The plurality of resistive films are arranged spaced apart in a second direction orthogonal to the first direction in plan view. The plurality of resistive films are divided into a first group, a second group, and a third group. The first group is located between the second group and the third group in the second direction. A second width variation amount of each of the plurality of second resistive films belonging to the second group and a third width variation amount of each of the plurality of third resistive films belonging to the third group are larger than a first width variation amount of each of the plurality of first resistive films belonging to the first group.
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公开(公告)号:US20170272088A1
公开(公告)日:2017-09-21
申请号:US15615719
申请日:2017-06-06
CPC分类号: H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
摘要: An analog-to-digital (AD) convertor includes: a capacitance digital-to-analog (DA) convertor circuit; a comparator circuit coupled to the capacitance DA convertor circuit; and a calibration circuit that calculates a correction value for the AD convertor, wherein the capacitance DA convertor circuit includes a first capacitor, a second capacitor, n number of capacitors (n being integer equal to or larger than 3), each of the capacitors from first to n-th to be activated based on input digital data, wherein each of the first and second capacitors is designed for having a first capacitance value, wherein the n-th capacitor is designed for having twice the capacitance value of the (n−1)-th capacitor, wherein the calibration circuit calculates the correction value based on first and second results of the AD convertor, and wherein the first result is generated using the n-th capacitor and the second result is generated using the capacitors from first to (n−1)-th.
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公开(公告)号:US20180267092A1
公开(公告)日:2018-09-20
申请号:US15987572
申请日:2018-05-23
CPC分类号: G01R31/025 , G01D5/12 , G01D5/24466 , H02H7/0833 , H02P6/12 , H02P6/16 , H03F3/45071 , H03F3/45475 , H03F2200/129 , H03F2200/231 , H03F2200/234 , H03F2200/261 , H03F2203/45116 , H03F2203/45138 , H03F2203/45171 , H03F2203/45528 , H03K3/017
摘要: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.
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公开(公告)号:US20180069563A1
公开(公告)日:2018-03-08
申请号:US15799034
申请日:2017-10-31
CPC分类号: H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
摘要: An analog-to-digital (AD) convertor includes: an AD conversion circuit; and a correction circuit that corrects an output value of the AD conversion circuit based on a correction value, wherein the correction circuit generates a plurality of elemental correction values based on a plurality of output values which are converted values of a plurality of analog values by the AD conversion circuit, wherein the correction value is determined by an average value of remaining values obtained by removing a deviated value from the plurality of elemental correction values.
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公开(公告)号:US20170257112A1
公开(公告)日:2017-09-07
申请号:US15390606
申请日:2016-12-26
发明人: Yoshihiro FUNATO , Yasuo MORIMOTO
CPC分类号: H03M1/466 , H03M1/06 , H03M1/0695 , H03M1/468
摘要: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
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