公开(公告)号：US09865555B2

公开(公告)日：2018-01-09

申请号：US15454230

申请日：2017-03-09

申请人： Texas Instruments Incorporated

发明人： Manoj K. Jain

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L24/05 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

公开(公告)号：US09793198B2

公开(公告)日：2017-10-17

申请号：US14275519

申请日：2014-05-12

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC分类号： H01L23/498 ,  B23K35/22 ,  B23K35/02 ,  B32B15/01 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  B23K1/00 ,  B23K101/40

CPC分类号： H01L23/49811 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/0266 ,  B23K35/22 ,  B23K2101/40 ,  B32B15/01 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/98 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/03001 ,  H01L2224/03009 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/03334 ,  H01L2224/0348 ,  H01L2224/03848 ,  H01L2224/03849 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0391 ,  H01L2224/04105 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05294 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/056 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/05855 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/2401 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/75253 ,  H01L2224/81 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8122 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2224/82105 ,  H01L2224/83 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

摘要： A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

公开(公告)号：US09627334B2

公开(公告)日：2017-04-18

申请号：US15278072

申请日：2016-09-28

申请人： Texas Instruments Incorporated

发明人： Manoj K. Jain

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

公开(公告)号：US20170018516A1

公开(公告)日：2017-01-19

申请号：US15278072

申请日：2016-09-28

申请人： Texas Instruments Incorporated

发明人： Manoj K. JAIN

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

摘要翻译： 一种集成电路，包括形成在电介质层中的连接开口中的顶部金属互连层上的自对准底部凸块金属焊盘，其中形成在自对准凸块上的金属焊盘上的焊球。 通过在互连层上形成一个或多个金属层和电介质层的方法，形成集成电路的方法，所述集成电路包括形成在电介质层的连接开口中的顶部金属互连层上的自对准的凸块下金属焊盘 从电介质层上除去金属，随后在自对准的凸块上的金属焊盘上形成焊球。 一些实例包括在选择性去除工艺之后形成的附加金属层，并且可以包括在附加金属层上的额外的选择性去除工艺。

公开(公告)号：US09478510B2

公开(公告)日：2016-10-25

申请号：US14559215

申请日：2014-12-03

申请人： Texas Instruments Incorporated

发明人： Manoj K. Jain

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

摘要翻译： 一种集成电路，包括形成在电介质层中的连接开口中的顶部金属互连层上的自对准底部凸块金属焊盘，其中形成在自对准凸块上的金属焊盘上的焊球。 通过在互连层上形成一个或多个金属层和电介质层的方法，形成集成电路的方法，所述集成电路包括形成在电介质层的连接开口中的顶部金属互连层上的自对准的凸块下金属焊盘 从电介质层上除去金属，随后在自对准的凸块上的金属焊盘上形成焊球。 一些实例包括在选择性去除工艺之后形成的附加金属层，并且可以包括在附加金属层上的额外的选择性去除工艺。

公开(公告)号：US09418955B2

公开(公告)日：2016-08-16

申请号：US14096435

申请日：2013-12-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34 ,  H05K3/40

CPC分类号： H01L24/13 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03831 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/3478 ,  H05K3/4007 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/1082

摘要： A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

摘要翻译： 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。

公开(公告)号：US20160099222A1

公开(公告)日：2016-04-07

申请号：US14955033

申请日：2015-11-30

申请人： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao Chung Foh ,  Zigmund Ramirez Camacho

发明人： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao Chung Foh ,  Zigmund Ramirez Camacho

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03001 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05664 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/3318

摘要： An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：提供基板; 在衬底的顶部形成接触垫; 在所述接触焊盘和所述衬底的顶部上形成保护层; 使接触垫从保护层露出; 在通过导电油墨在保护层上延伸的暴露的接触垫上印刷凸块下金属化（UBM）层; 以及在凸起下金属化层的顶部上形成凸块。 它还包括：使用导电油墨印刷粘合层，其中粘合层包括相互连接的粘合层垫; 使用电沉积工艺在所述粘附层垫的顶部上形成附加的凹凸金属化（UBM）层和凸块; 以及去除互连的粘合层垫中的连接。

公开(公告)号：US09202793B1

公开(公告)日：2015-12-01

申请号：US14140829

申请日：2013-12-26

申请人： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao ,  Zigmund Ramirez Camacho

发明人： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao ,  Zigmund Ramirez Camacho

IPC分类号： H01L21/60 ,  H01L23/00

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03001 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05664 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/3318

摘要： An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：提供基板; 在衬底的顶部形成接触垫; 在所述接触焊盘和所述衬底的顶部上形成保护层; 使接触垫从保护层露出; 在通过导电油墨在保护层上延伸的暴露的接触垫上印刷凸块下金属化（UBM）层; 以及在凸起下金属化层的顶部上形成凸块。 它还包括：使用导电油墨印刷粘合层，其中粘合层包括相互连接的粘合层垫; 使用电沉积工艺在所述粘附层垫的顶部上形成附加的凹凸金属化（UBM）层和凸块; 以及去除互连的粘合层垫中的连接。

公开(公告)号：US09070675B2

公开(公告)日：2015-06-30

申请号：US13973492

申请日：2013-08-22

申请人： Kwang Sup So ,  No Sun Park

发明人： Kwang Sup So ,  No Sun Park

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/525

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/562 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/0231 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A plating structure for wafer level packages are disclosed and may include a semiconductor wafer comprising a plurality of semiconductor die and a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die. The plating structure may comprise a plating connection line around a periphery of the semiconductor wafer, and a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die. The plating traces may be electrically coupled to the redistribution layers on the plurality of semiconductor die. The semiconductor wafer may comprise a reconstituted wafer of said semiconductor die. The semiconductor wafer may comprise a wafer prior to singulating the plurality of semiconductor die. The plating bar may be located in a sawing line for the singulating of the plurality of semiconductor die. A passivation layer may cover the redistribution layer and the plating traces.

摘要翻译： 公开了一种用于晶片级封装的电镀结构，并且可以包括半导体晶片，该半导体晶片包括多个半导体管芯和用于在多个半导体管芯上的再分配层上形成凸块状金属的电镀结构。 电镀结构可以包括围绕半导体晶片的周围的电镀连接线，以及将电镀连接线耦合到多个半导体管芯上的电镀迹线的电镀棒。 电镀迹线可以电耦合到多个半导体管芯上的再分配层。 半导体晶片可以包括所述半导体管芯的重构晶片。 在分离多个半导体管芯之前，半导体晶片可以包括晶片。 电镀棒可以位于用于单个多个半导体管芯的锯切线中。 钝化层可以覆盖再分布层和电镀痕迹。

公开(公告)号：US09059158B2

公开(公告)日：2015-06-16

申请号：US14335084

申请日：2014-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Chih-Horng Chang

IPC分类号： H01L23/02 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/535

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/535 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03424 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03848 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2924/01046 ,  H01L2924/01039 ,  H01L2924/01016 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2224/034 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device comprises a semiconductor substrate, an under-bump metallization (UBM) structure overlying the semiconductor substrate, and a solder bump overlying and electrically connected to the UBM structure. The UBM structure comprises a first metallization layer comprising a first metal, a second metallization layer comprising a second metal different from the first metal, and a first intermetallic compound (IMC) layer between the first metallization layer and the second metallization layer, the first IMC layer comprising the first metal and the second metal.

摘要翻译： 半导体器件包括半导体衬底，覆盖半导体衬底的凸起下金属化（UBM）结构以及覆盖并电连接到UBM结构的焊料凸块。 UBM结构包括第一金属化层，其包括第一金属，第二金属化层，第二金属化层包括不同于第一金属的第二金属，以及在第一金属化层和第二金属化层之间的第一金属间化合物（IMC）层，第一IMC 层，其包含第一金属和第二金属。