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公开(公告)号：US20170018516A1
公开(公告)日：2017-01-19
申请号：US15278072
申请日：2016-09-28
发明人： Manoj K. JAIN
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L23/528 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0361 , H01L2224/03614 , H01L2224/03616 , H01L2224/03622 , H01L2224/03901 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05172 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05547 , H01L2224/05557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05671 , H01L2224/1132 , H01L2224/11334 , H01L2224/1146 , H01L2224/11462 , H01L2224/13007 , H01L2224/13014 , H01L2224/13016 , H01L2224/13023 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13139 , H01L2224/81815 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3651 , H01L2924/00014 , H01L2924/01023 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029
摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.
摘要翻译： 一种集成电路，包括形成在电介质层中的连接开口中的顶部金属互连层上的自对准底部凸块金属焊盘，其中形成在自对准凸块上的金属焊盘上的焊球。 通过在互连层上形成一个或多个金属层和电介质层的方法，形成集成电路的方法，所述集成电路包括形成在电介质层的连接开口中的顶部金属互连层上的自对准的凸块下金属焊盘 从电介质层上除去金属，随后在自对准的凸块上的金属焊盘上形成焊球。 一些实例包括在选择性去除工艺之后形成的附加金属层，并且可以包括在附加金属层上的额外的选择性去除工艺。
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公开(公告)号：US20170179053A1
公开(公告)日：2017-06-22
申请号：US15454230
申请日：2017-03-09
发明人： Manoj K. JAIN
IPC分类号： H01L23/00 , H01L23/528
CPC分类号： H01L24/05 , H01L23/528 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0361 , H01L2224/03614 , H01L2224/03616 , H01L2224/03622 , H01L2224/03901 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05172 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05547 , H01L2224/05557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05671 , H01L2224/1132 , H01L2224/11334 , H01L2224/1146 , H01L2224/11462 , H01L2224/13007 , H01L2224/13014 , H01L2224/13016 , H01L2224/13023 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13139 , H01L2224/81815 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3651 , H01L2924/00014 , H01L2924/01023 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029
摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.
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公开(公告)号：US20150179592A1
公开(公告)日：2015-06-25
申请号：US14559215
申请日：2014-12-03
发明人： Manoj K. JAIN
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L23/528 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0361 , H01L2224/03614 , H01L2224/03616 , H01L2224/03622 , H01L2224/03901 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05172 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05547 , H01L2224/05557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05671 , H01L2224/1132 , H01L2224/11334 , H01L2224/1146 , H01L2224/11462 , H01L2224/13007 , H01L2224/13014 , H01L2224/13016 , H01L2224/13023 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13139 , H01L2224/81815 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3651 , H01L2924/00014 , H01L2924/01023 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029
摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.
摘要翻译： 一种集成电路，包括形成在电介质层中的连接开口中的顶部金属互连层上的自对准底部凸块金属焊盘，其中形成在自对准凸块上的金属焊盘上的焊球。 通过在互连层上形成一个或多个金属层和电介质层的方法，形成集成电路的方法，所述集成电路包括形成在电介质层的连接开口中的顶部金属互连层上的自对准的凸块下金属焊盘 从电介质层上除去金属，随后在自对准的凸块上的金属焊盘上形成焊球。 一些实例包括在选择性去除工艺之后形成的附加金属层，并且可以包括在附加金属层上的额外的选择性去除工艺。
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