公开(公告)号：US20240387432A1

公开(公告)日：2024-11-21

申请号：US18786615

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Fu Tsai ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

Abstract: A package structure includes a semiconductor die, a first insulating encapsulant, a plurality of first conductive features, an interconnect structure and bump structures. The semiconductor die includes a plurality of conductive pillars made of a first material. The first insulating encapsulant is encapsulating the semiconductor die. The first conductive features are disposed on the semiconductor die and electrically connected to the conductive pillars. The first conductive features include at least a second material different from the first material. The interconnect structure is disposed on the first conductive features, wherein the interconnect structure includes a plurality of connection structures made of the second material. The bump structures are electrically connecting the first conductive features to the connection structures, wherein the bump structures include a third material different from the first material and the second material.

公开(公告)号：US12119324B2

公开(公告)日：2024-10-15

申请号：US17963181

申请日：2022-10-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kung-Chen Yeh ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih

IPC: H01L23/00 ,  H01L21/268 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/94 ,  H01L21/268 ,  H01L21/3043 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/13 ,  H01L24/97 ,  H01L25/0652

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

公开(公告)号：US20240339415A1

公开(公告)日：2024-10-10

申请号：US18743027

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Fu Tsai ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/50

Abstract: A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.

公开(公告)号：US20240105629A1

公开(公告)日：2024-03-28

申请号：US18523895

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hsuan Tsai ,  Chin-Chuan Chang ,  Szu-Wei Lu ,  Tsung-Fu Tsai

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/5226 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/02372

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.

公开(公告)号：US20240021442A1

公开(公告)日：2024-01-18

申请号：US18362992

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun-Ting Chen ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih ,  Ting-Yu Yeh ,  Chen-Hsuan Tsai

IPC: H01L21/56 ,  H01L21/304 ,  H01L23/13 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L21/561 ,  H01L21/3043 ,  H01L23/13 ,  H01L23/3135 ,  H01L25/0655 ,  H01L25/18 ,  H01L21/563 ,  H01L23/147

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

公开(公告)号：US10453818B2

公开(公告)日：2019-10-22

申请号：US15881022

申请日：2018-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Fu Tsai ,  Chia-Wei Tu ,  Yian-Liang Kuo ,  Ru-Ying Huang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/58 ,  H01L25/065

Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.

公开(公告)号：US10269762B2

公开(公告)日：2019-04-23

申请号：US14926780

申请日：2015-10-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih Ting Lin ,  Justin Huang ,  Tsung-Fu Tsai ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: B23K31/02 ,  H01L23/00 ,  B23K1/005 ,  B23K1/012 ,  B23K1/018 ,  B23K1/20 ,  B23K3/02 ,  B23K1/00

Abstract: A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.

公开(公告)号：US20170256512A1

公开(公告)日：2017-09-07

申请号：US15601801

申请日：2017-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

公开(公告)号：US09548245B2

公开(公告)日：2017-01-17

申请号：US14724954

申请日：2015-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Tsung-Fu Tsai ,  Min-Feng Ku

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/82 ,  H01L21/56 ,  H01L21/304 ,  H01L23/31

CPC classification number: H01L23/3121 ,  H01L21/304 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00

Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.

Abstract translation: 一种装置包括第一包装部件和第二包装部件，所述第一包装部件和第二包装部件下面并结合到第一包装部件。 成型材料设置在第一包装部件下方并被模制到第一和第二包装部件上，其中成型材料和第一包装部件形成界面。 隔离区域包括第一边缘，其中隔离区域的第一边缘接触第一封装部件的第一边缘和模制材料的第一边缘。 隔离层的底部低于界面。

公开(公告)号：US20160005704A1

公开(公告)日：2016-01-07

申请号：US14853006

申请日：2015-09-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.