公开(公告)号：US20150270247A1

公开(公告)日：2015-09-24

申请号：US14447426

申请日：2014-07-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Jie Chen ,  Der-Chyang Yeh ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/02319 ,  H01L2224/03438 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11332 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/01082 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/2064 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01074

摘要： Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

摘要翻译： 本公开的实施例包括半导体封装及其形成方法。 一个实施例是一种半导体封装，其包括包括一个或多个管芯的第一封装，以及在第一封装的第一侧处与第一组接合接头耦合到一个或多个管芯的再分配层。 再分配层包括设置在多于一个钝化层中的多于一个金属层，第一组接合接头直接耦合到一个或多个金属层中的至少一个，以及耦合到第一组连接器 再分配层，第二侧与第一侧相对。

公开(公告)号：US09129944B2

公开(公告)日：2015-09-08

申请号：US14456411

申请日：2014-08-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/34 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/80895 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00

摘要： A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. One of the device die and the plurality of dies includes a semiconductor substrate and a through-via penetrating through the semiconductor substrate, A polymer region includes portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first and the second plurality of metal pillars. Redistribution lines are formed over the first and the second plurality of metal pillars.

摘要翻译： 包装包括在器件裸片的顶表面上包括第一多个金属柱的器件裸片。 该封装还包括一个管芯堆叠，该管芯堆叠包括多个结合在一起的管芯，以及在管芯叠层的顶表面处的第二多个金属柱。 所述器件管芯和所述多个管芯中的一个包括半导体衬底和穿过所述半导体衬底的穿通孔。聚合物区域包括环绕所述器件管芯和所述管芯堆叠的部分，其中所述聚合物区域的底表面基本上是水平的 具有器件的底表面和管芯堆叠的底表面。 聚合物区域的顶表面与第一和第二多个金属柱的顶端平齐。 再分配线形成在第一和第二多个金属柱上。

公开(公告)号：US20150206871A1

公开(公告)日：2015-07-23

申请号：US14673388

申请日：2015-03-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Der-Chyang Yeh ,  Hsing-Kuo Hsia ,  Hao-Hsun Lin ,  Chih-Ping Chao ,  Chin-Hao Su ,  Hsi-Kuei Cheng

IPC分类号： H01L27/06 ,  H01L29/45

CPC分类号： H01L27/0623 ,  H01L21/28518 ,  H01L21/8249 ,  H01L29/45

摘要： A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.

摘要翻译： 提供了一种提供多重硅化物整合的结构和方法。 一个实施例包括在衬底上形成第一晶体管和第二晶体管。 第一晶体管被掩蔽，并且在第二晶体管上形成第一硅化物区。 然后对第二晶体管进行掩模，并且在第一晶体管上形成第二硅化物区域，从而允许在独立器件上形成器件特定的硅化物区域。

公开(公告)号：US20150115464A1

公开(公告)日：2015-04-30

申请号：US14147316

申请日：2014-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh ,  Kuo-Chung Yee ,  Jui-Pin Hung

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/48

CPC分类号： H01L25/0652 ,  H01L21/0273 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11616 ,  H01L2224/11622 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2924/00012

摘要： A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

摘要翻译： 提供一种用于封装半导体器件的系统和方法。 一个实施例包括在载体晶片上形成通孔并将第一裸片附着在载体晶片上并且在前两个通孔之间。 第二管芯附着在载体晶片上并且在第二个两个通孔之间。 第一管芯和第二管芯被封装以形成第一封装，并且至少一个第三管芯连接到第一管芯或第二管芯。 第二包装通过至少一个第三管芯连接到第一包装。

公开(公告)号：US20150084191A1

公开(公告)日：2015-03-26

申请号：US14561678

申请日：2014-12-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Chen-Hua Yu ,  Jui-Pin Hung ,  Der-Chyang Yeh

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/183 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/01047 ,  H01L2224/82 ,  H01L2924/00

摘要： A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures.

摘要翻译： 一种器件包括嵌入在模塑复合层中的第一半导体管芯，嵌入在模塑料层中的表面安装器件，形成在模塑复合层上的多个互连结构，其中第一半导体管芯电耦合到互连结构 并且所述表面贴装器件通过至少金属柱和形成在所述互连结构上并电耦合到所述互连结构的多个凸起电耦合到所述互连结构。

公开(公告)号：US08927412B1

公开(公告)日：2015-01-06

申请号：US13956601

申请日：2013-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Chen-Hua Yu ,  Jui-Pin Hung ,  Der-Chyang Yeh

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/14 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/183 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/01047 ,  H01L2224/82 ,  H01L2924/00

摘要： A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures.

摘要翻译： 一种器件包括嵌入在模塑复合层中的第一半导体管芯，嵌入在模塑料层中的表面安装器件，形成在模塑复合层上的多个互连结构，其中第一半导体管芯电耦合到互连结构 并且所述表面贴装器件通过至少金属柱和形成在所述互连结构上并电耦合到所述互连结构的多个凸起电耦合到所述互连结构。

公开(公告)号：US20140367160A1

公开(公告)日：2014-12-18

申请号：US14472681

申请日：2014-08-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC分类号： H05K9/00

CPC分类号： H01L23/552 ,  H01L21/32051 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/585 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line.

摘要翻译： 包装包括装置模具，模制其中的装置模具的模制材料和穿过模制材料的穿通孔。 再分配线位于成型材料的一侧。 再分配线电连接到通孔。 金属环靠近封装的边缘，其中金属环与再分布线共面。

公开(公告)号：US20140319696A1

公开(公告)日：2014-10-30

申请号：US14265278

申请日：2014-04-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh

IPC分类号： H01L23/00

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82001 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： Embodiments of the present disclosure include a semiconductor device, a package, and methods of forming a semiconductor device and a package. An embodiment is a method including placing a plurality of dies over a passivation layer, the plurality of dies comprising at least one active device, molding the plurality of dies with a first molding material, and forming a plurality of through-package vias (TPVs) in the first molding material, first surfaces of the plurality of TPVs being substantially coplanar with a backside surfaces of the plurality of dies. The method further includes patterning the passivation layer to expose a portion of the first surfaces of the plurality of TPVs, and bonding a plurality of top packages to the first surfaces of the plurality of TPVs.

摘要翻译： 本公开的实施例包括半导体器件，封装以及形成半导体器件和封装的方法。 一个实施例是一种方法，包括将多个模具放置在钝化层上，所述多个模具包括至少一个有源装置，用第一模制材料模制多个模具，以及形成多个通过包装通孔（TPV） 在第一模塑材料中，多个TPV的第一表面与多个模具的背面大致共面。 该方法还包括图案化钝化层以暴露多个TPV的第一表面的一部分，以及将多个顶部封装结合到多个TPV的第一表面。

公开(公告)号：US20140252572A1

公开(公告)日：2014-09-11

申请号：US13791305

申请日：2013-03-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shang-Yun Hou ,  Der-Chyang Yeh ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L23/3157 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014

摘要： Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive elements, adding an underfill between the second dies and the first dies surrounding the conductive elements, and encapsulating in a second molding compound the second dies and the underfill. The chip package comprises a chip encapsulated in a molding compound, and a larger chip coupled to the first chip via conductive elements, wherein the conductive elements are encapsulated in an underfill between the chip and the larger chip without an interposer, and wherein the larger chip and the underfill are encapsulated in a second molding compound in contact with the molding compound.

摘要翻译： 提供了一种芯片封装结构和用于形成芯片封装的方法。 该方法包括：将多个第一模具结合在载体上，将第一模具封装在载体上的第一模具中，使用导电元件将第一模具上的多个第二模具连接起来，在第二模具与第一模具之间加入底部填充物 围绕导电元件的模具，并且将第二模具和底部填充物封装在第二模塑复合物中。 芯片封装包括封装在模制化合物中的芯片，以及通过导电元件耦合到第一芯片的较大芯片，其中导电元件封装在芯片和较大芯片之间的底部填充物，而没有插入器，并且其中较大芯片 并将底部填充物封装在与模塑料接触的第二模塑料中。

公开(公告)号：US20240355721A1

公开(公告)日：2024-10-24

申请号：US18761200

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Li-Hsien Huang ,  An-Jhih Su ,  Der-Chyang Yeh ,  Hua-Wei Tseng ,  Chiang Lin ,  Ming-Shih Yeh

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/105 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A semiconductor package includes a semiconductor die including an active surface and an electrical terminal on the active surface, and a redistribution circuitry disposed on the active surface of the semiconductor die and connected to the electrical terminal. A top surface of the redistribution circuitry includes a planar portion and a concave portion connected to the planar portion, the concave portion is directly over the electrical terminal, and a minimum distance measured from a lowest point of the concave portion to a virtual plane where the planar portion is located is equal to or smaller than 0.5 μm.