公开(公告)号：US20240250163A1

公开(公告)日：2024-07-25

申请号：US18429202

申请日：2024-01-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B63/00 ,  H10B69/00

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

公开(公告)号：US12048168B2

公开(公告)日：2024-07-23

申请号：US17721932

申请日：2022-04-15

Applicant: SK hynix Inc.

Inventor： Ki Hong Lee

IPC: H10B69/00 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B69/00 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/00 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: A semiconductor device may include a source layer, a stack structure, a channel layer, a slit, and a source pick-up line. The source layer may include at least one groove in an upper surface thereof. The stack structure may be formed over the source layer. The channel layer may pass through the stack structure. The channel layer may be in contact with the source layer. The slit may pass through the stack structure. The slit may expose the groove of the source layer therethrough. The source pick-up line may be formed in the slit and the groove. The source pick-up line may be contacted with the source layer.

公开(公告)号：US20240237366A9

公开(公告)日：2024-07-11

申请号：US18487248

申请日：2023-10-16

Applicant: ROHM CO., LTD.

Inventor： Takeharu IMAI

IPC: H10B99/00 ,  H10B69/00

CPC classification number: H10B99/14 ,  H10B69/00

Abstract: A semiconductor integrated circuit device includes: a terminal; an internal resistor that is any one of a pull-up resistor configured so that a first end of the pull-up resistor is connected to the terminal and a first constant voltage is applied to a second end of the pull-up resistor, or a pull-down resistor configured so that a first end of the pull-down resistor is connected to the terminal and a ground voltage is applied to a second end of the pull-down resistor; and an AD converter configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more.

公开(公告)号：US12033704B2

公开(公告)日：2024-07-09

申请号：US17952659

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Junya Matsuno ,  Kenro Kubota ,  Masato Dome ,  Kensuke Yamamoto ,  Kei Shiraishi ,  Kazuhiko Satou ,  Ryo Fukuda ,  Masaru Koyanagi

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.

公开(公告)号：US12021028B2

公开(公告)日：2024-06-25

申请号：US18389582

申请日：2023-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B10/00 ,  H10B12/00 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B10/125 ,  H10B12/37 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L2225/06541

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

公开(公告)号：US11963374B2

公开(公告)日：2024-04-16

申请号：US17582092

申请日：2022-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H10B99/00 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/16 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L21/822 ,  H01L27/06 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B99/00 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/7833 ,  H10B12/00

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US11956977B2

公开(公告)日：2024-04-09

申请号：US17462181

申请日：2021-08-31

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Jan Willem Maes

IPC: H10B69/00 ,  H01L21/02 ,  H01L49/02 ,  H10B41/27 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B69/00 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02658 ,  H01L28/00 ,  H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method for forming a V-NAND device is disclosed. Specifically, the method involves deposition of at least one of semiconductive material, conductive material, or dielectric material to form a channel for the V-NAND device. In addition, the method may involve a pretreatment step where ALD, CVD, or other cyclical deposition processes may be used to improve adhesion of the material in the channel.

公开(公告)号：US11937437B2

公开(公告)日：2024-03-19

申请号：US17381911

申请日：2021-07-21

Applicant: Kioxia Corporation

Inventor： Masahiro Kiyotoshi ,  Akihito Yamamoto ,  Yoshio Ozawa ,  Fumitaka Arai ,  Riichiro Shirota

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US11935949B1

公开(公告)日：2024-03-19

申请号：US18388852

申请日：2023-11-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B63/00 ,  H10B69/00

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

公开(公告)号：US11922108B2

公开(公告)日：2024-03-05

申请号：US17504805

申请日：2021-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Hsiang Weng ,  Yu-Der Chih

IPC: G06F30/39 ,  G11C13/00 ,  H10B61/00 ,  H10B63/00 ,  H10B69/00 ,  G06F30/392 ,  G06F30/394 ,  H10N70/00

CPC classification number: G06F30/39 ,  G11C13/003 ,  H10B61/22 ,  H10B63/30 ,  H10B63/80 ,  H10B69/00 ,  G06F30/392 ,  G06F30/394 ,  G11C2213/79 ,  H10N70/826 ,  H10N70/841

Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.