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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11495307B2

    公开(公告)日：2022-11-08

    申请号：US17202590

    申请日：2021-03-16

    Applicant: Kioxia Corporation

    Inventor： Masato Dome ,  Kensuke Yamamoto ,  Masaru Koyanagi ,  Ryo Fukuda ,  Junya Matsuno ,  Kenro Kubota

    IPC: G11C16/04 ,  G11C16/30

    Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

    Output circuit
    3.
    发明授权
    Output circuit 有权

    公开(公告)号：US11380406B2

    公开(公告)日：2022-07-05

    申请号：US17017726

    申请日：2020-09-11

    Applicant: Kioxia Corporation

    Inventor： Yousuke Hagiwara ,  Kensuke Yamamoto ,  Takeshi Hioka ,  Satoshi Inoue

    IPC: G11C7/00 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

    Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11495308B2

    公开(公告)日：2022-11-08

    申请号：US17202661

    申请日：2021-03-16

    Applicant: Kioxia Corporation

    Inventor： Junya Matsuno ,  Kenro Kubota ,  Masato Dome ,  Kensuke Yamamoto ,  Kei Shiraishi ,  Kazuhiko Satou ,  Ryo Fukuda ,  Masaru Koyanagi

    IPC: G11C16/32 ,  G11C16/04 ,  H01L27/115 ,  G11C16/08 ,  G11C16/26

    Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.

    Memory device
    9.
    发明授权
    Memory device 有权

    公开(公告)号：US12034443B2

    公开(公告)日：2024-07-09

    申请号：US18125081

    申请日：2023-03-22

    Applicant: Kioxia Corporation

    Inventor： Junya Matsuno ,  Kensuke Yamamoto ,  Ryo Fukuda ,  Masaru Koyanagi ,  Kenro Kubota ,  Masato Dome

    IPC: G11C7/10 ,  G11C7/06 ,  G11C11/419 ,  H03K19/0185

    CPC classification number: H03K19/018521 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  H03K19/018571 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/419

    Abstract: A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.

    Memory system
    10.
    发明授权
    Memory system 有权

    公开(公告)号：US12135898B2

    公开(公告)日：2024-11-05

    申请号：US18520612

    申请日：2023-11-28

    Applicant: Kioxia Corporation

    Inventor： Kensuke Yamamoto

    IPC: G11C7/22 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10

    Abstract: A semiconductor memory device includes a memory cell storing data; a signal pad inputting write data to the memory cell and from which read data read from the memory cell is output to an external controller; a first control pad receiving a first timing control signal from the external controller; and a second control pad outputting a second timing control signal to the external controller. In a first time period after a data out command is received, dummy data are output from the signal pad while the second timing control signal from the second control pad is toggling in response to toggling of the first timing control signal input to the first control pad. In a second time period after the first time period, read data are output from the signal pad while the second timing control signal is toggling in response to toggling of the first timing control signal.

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