公开(公告)号：US11923840B1

公开(公告)日：2024-03-05

申请号：US18180167

申请日：2023-03-08

申请人： NXP B.V.

发明人： Chinmayee Kumari Panigrahi ,  Sunil Chandra Kasanyal ,  Shashank Sunil Amati

IPC分类号： G06F1/24 ,  G06F1/28 ,  H03K17/687 ,  H03K19/0185

CPC分类号： H03K17/6872 ,  G06F1/28 ,  H03K19/018571

摘要： A power down signal generator generates a power down signal. The power down signal generator includes a detection transistor, a resistor coupled in series with the detection transistor, and a compensation transistor coupled in parallel to the resistor. The detection transistor receives a first supply voltage in a first voltage domain and a current. A control voltage is generated across the resistor based on a first part of the current. The compensation transistor receives a bias voltage derived from a second supply voltage in a second voltage domain and sinks, based on the bias voltage, a second part of the current to maintain the control voltage within a predefined range. The generation of the power down signal is controlled based on the first supply voltage and the control voltage.

公开(公告)号：US20230411390A1

公开(公告)日：2023-12-21

申请号：US17842462

申请日：2022-06-16

申请人： Intel Corporation

发明人： Kevin P. O'Brien ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Rachel A. Steinhardt ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci ,  Chelsey Dorow

IPC分类号： H01L27/092 ,  H03K19/0185 ,  H01L29/26 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L27/092 ,  H03K19/018571 ,  H01L29/26 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5283

摘要： In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).

公开(公告)号：US11843374B2

公开(公告)日：2023-12-12

申请号：US17830056

申请日：2022-06-01

申请人： SK hynix Inc.

发明人： Seung Ho Lee

IPC分类号： H03K19/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/003

CPC分类号： H03K19/018521 ,  H03K3/356113 ,  H03K3/356182 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/018571

摘要： A level shifter may include: a discharge circuit configured to receive an input signal on the basis of a first power supply voltage, and discharge an internal node on the basis of the input signal; a charge supply circuit configured to supply charge to an output node from which an output signal is outputted, on the basis of a second power supply voltage; and a voltage adjustment circuit including a first MOS transistor coupled between the internal node and the output node, and configured to adjust the voltage of the output node on the basis of a bias voltage applied to the first MOS transistor, and stop the operation of adjusting the voltage of the output node on the basis of the bias voltage, when the levels of the first and second power supply voltages are equal to each other.

公开(公告)号：US20180309450A1

公开(公告)日：2018-10-25

申请号：US15769465

申请日：2016-07-27

申请人： SONY CORPORATION

发明人： YUKI YAGISHITA

IPC分类号： H03K19/0185 ,  H03M1/38 ,  H03K17/30

CPC分类号： H03K19/018571 ,  H03K17/04123 ,  H03K17/302 ,  H03K19/0185 ,  H03K19/018507 ,  H03M1/38 ,  H03M1/74

摘要： An operation speed of a voltage conversion circuit is improved without increasing an output level of the voltage conversion circuit. The voltage conversion circuit is provided with a high-voltage side transistor and a gate control unit. In this voltage conversion circuit, the high-voltage side transistor outputs a predetermined high voltage higher than a predetermined reference voltage. Also, in the voltage conversion circuit, the gate control unit generates a predetermined control voltage higher than a predetermined high voltage from an input signal and applies the same between a gate and a source of the high-voltage side transistor, thereby allowing the high-voltage side transistor to output a predetermined high voltage.

公开(公告)号：US09934747B2

公开(公告)日：2018-04-03

申请号：US15496061

申请日：2017-04-25

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Jun Koyama ,  Atsushi Umezaki

IPC分类号： H03K5/00 ,  G09G3/36 ,  H01L27/12 ,  H01L27/02 ,  G11C19/00

CPC分类号： G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  H01L27/0207 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/687 ,  H03K19/0013 ,  H03K19/018557 ,  H03K19/018571

摘要： The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

公开(公告)号：US20180083625A1

公开(公告)日：2018-03-22

申请号：US15270174

申请日：2016-09-20

申请人： QUALCOMM Incorporated

发明人： Manish Garg

IPC分类号： H03K19/00 ,  H03K19/0185 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08 ,  G11C7/06

CPC分类号： H03K19/0013 ,  G11C5/147 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  H03K19/018507 ,  H03K19/018521 ,  H03K19/018571

摘要： Voltage level shifter (VLS) circuits employing a pre-conditioning circuit for pre-conditioning an input signal to be voltage level shifted in response to a pre-charge phase are disclosed. A VLS circuit is configured to voltage level shift an input signal in a lower voltage domain on an output node in a higher voltage domain. The VLS circuit includes a pre-charge circuit configured to pre-charge the output node in a pre-charge phase. The VLS circuit also includes a pull-up circuit and a pull-down circuit that are configured to pull-up and pull-down the pre-charge phase of the output node, respectively, in an evaluation phase based on a logic state of the input signal to generate the output signal. To mitigate or avoid contention between the pull-up and pull-down circuits in the evaluation phase, the input signal is pre-conditioned such that the pull-down circuit is deactivated in response to the pre-charge phase.

公开(公告)号：US09830878B2

公开(公告)日：2017-11-28

申请号：US15175189

申请日：2016-06-07

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Jun Koyama ,  Atsushi Umezaki

IPC分类号： H03K3/00 ,  G09G3/36 ,  H01L27/02 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0185

CPC分类号： G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  H01L27/0207 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/687 ,  H03K19/0013 ,  H03K19/018557 ,  H03K19/018571

摘要： The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

公开(公告)号：US20170338821A1

公开(公告)日：2017-11-23

申请号：US15599815

申请日：2017-05-19

申请人： Rohm Co., Ltd.

发明人： Satoshi Tanaka

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/0948

CPC分类号： H03K19/00361 ,  H03K19/0013 ,  H03K19/0027 ,  H03K19/018521 ,  H03K19/018571 ,  H03K19/0948

摘要： A CMOS output circuit includes a first P-MOSFET having a source connected to a power supply terminal, a drain connected to an output terminal, and a back gate connected to a first potential terminal; a first N-MOSEFET having a drain connected to the output terminal, a source connected to the ground terminal, and a back gate connected to a second potential terminal; a first potential switching portion arranged to switch whether to connect the first potential terminal to the power supply terminal or to the output terminal; a second potential switching portion arranged to switch whether to connect the second potential terminal to the ground terminal or to the output terminal; a first gate switching portion arranged to switch whether or not to short-circuit the gate of the first P-MOSFET to the first potential terminal; a second gate switching portion arranged to switch whether or not to short-circuit the gate of the first N-MOSFET to the second potential terminal; a first driver arranged to drive the gate of the first P-MOSFET in accordance with a first input signal; a second driver arranged to drive the gate of the first N-MOSFET in accordance with a second input signal; and a control portion arranged to control individual portions of the circuit when turning off both the first P-MOSFET and the first N-MOSFET, so as to connect the first potential terminal to one of the power supply terminal and the output terminal, which has a higher potential, to connect the second potential terminal to one of the ground terminal and the output terminal, which has a lower potential, to short-circuit the gate of the first P-MOSFET to the first potential terminal, and to short-circuit the gate of the first N-MOSFET to the second potential terminal.

公开(公告)号：US20160293129A1

公开(公告)日：2016-10-06

申请号：US15175189

申请日：2016-06-07

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Jun KOYAMA ,  Atsushi UMEZAKI

IPC分类号： G09G3/36 ,  H01L29/786 ,  H03K19/00 ,  H03K17/687 ,  H03K19/0185 ,  H01L27/12 ,  H01L27/02

CPC分类号： G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  H01L27/0207 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/687 ,  H03K19/0013 ,  H03K19/018557 ,  H03K19/018571

摘要： The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

公开(公告)号：US09368519B2

公开(公告)日：2016-06-14

申请号：US14522817

申请日：2014-10-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Jun Koyama ,  Atsushi Umezaki

IPC分类号： H03L5/00 ,  H01L27/12 ,  H03K19/00 ,  H03K19/0185 ,  H03K17/687

CPC分类号： G09G3/3677 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  H01L27/0207 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/687 ,  H03K19/0013 ,  H03K19/018557 ,  H03K19/018571

摘要： The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.