公开(公告)号：US11881270B2

公开(公告)日：2024-01-23

申请号：US17693948

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yousuke Hagiwara

IPC: G11C16/32

CPC classification number: G11C16/32

Abstract: According to one embodiment, a detection circuit includes a first filter circuit configured to output a first voltage, a ramp circuit configured to output a ramp voltage, a comparator configured to output a first result of comparison between the first voltage and the ramp voltage and a second result of comparison between a second voltage and the ramp voltage, and a controller, wherein the controller determines a first period of time between a time when the ramp voltage output is started and a time when a magnitude correlation between the first voltage and the ramp voltage is inverted, and determines a second period of time between a time when the ramp voltage output is started and a time when a magnitude correlation between the second voltage and the ramp voltage is inverted.

公开(公告)号：US11380406B2

公开(公告)日：2022-07-05

申请号：US17017726

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Yousuke Hagiwara ,  Kensuke Yamamoto ,  Takeshi Hioka ,  Satoshi Inoue

IPC: G11C7/00 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

公开(公告)号：US12197732B2

公开(公告)日：2025-01-14

申请号：US17898370

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Kenta Shibasaki ,  Yoshihiko Shindo ,  Yasuhiro Hirashima ,  Akio Sugahara ,  Shigeki Nagasaka ,  Dai Nakamura ,  Yousuke Hagiwara

IPC: G06F3/06

Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

公开(公告)号：US12106811B2

公开(公告)日：2024-10-01

申请号：US17882459

申请日：2022-08-05

Applicant: Kioxia Corporation

Inventor： Yousuke Hagiwara ,  Kei Shiraishi

IPC: G11C7/00 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a comparator that outputs a signal switched in synchronism with a read enable signal from outside and outputs the signal, and a correction circuit that adjusts the duty cycle of the signal. The correction circuit includes a variable current source connected to a first output portion of the comparator, and a variable current source connected to a second output portion of the comparator, and adjusts the amounts of current output from the current sources to adjust the duty cycles of signals.